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參數(shù)資料
| 型號(hào)： | LCK4953 |
| 英文描述： | Low-Voltage PLL Clock Driver |
| 中文描述： | 低電壓PLL時(shí)鐘驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 5/6頁(yè) |
| 文件大?。?/td> | 98K |
| 代理商： | LCK4953 |
Agere Systems Inc.
5
Data Sheet
November 2001
Low-Voltage PLL Clock Driver
LCK4953
Electrical Characteristics
(continued)
Driving Transmission Lines
The LCK4953 clock driver was designed to drive high-speed clock terminals in a terminated transmission line
environment. Point-to-point distribution of signals is a common method in most high-performance clock networks.
Either series-terminated or parallel-terminated transmission lines can be used in a point-to-point scheme. The
parallel technique terminates the signal at the end of a line with a 50
resistance to V
DD
/2. This draws a fairly high
level of dc current. Due to this aspect, only a single terminated line can be driven by each output of the LCK4953
clock driver. For the series-terminated case, however, there is no dc current draw; in turn, the outputs are capable
of driving multiple series-terminated lines.
Figure 4 illustrates an output driving a single series-terminated line.
5-9576(F)
Figure 4. Single Transmission Line
In Figure 4, because the output buffer has an impedance of 14
, the series resistance (R
s
) is set at 36
.
This
ensures that the total impedance is matched with the 50
transmission line.
Figure 5 illustrates an output driving two series-terminated lines.
5-9577(F)
Figure 5. Dual Transmission Lines
In Figure 5, the two series resistors (R
s)
are set at 22
because the 14
output buffer can be viewed as two 28
resistors in parallel. Accordingly, for each transmission line, the impedance is well matched.
OUTPUT
CLOCK
OUTPUT
BUFFER
14
R
S
= 36
Z
O
= 50
OUTPUT
CLOCK
OUTPUT
BUFFER
14
R
S
= 22
Z
O
= 50
R
S
= 22
Z
O
= 50
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| LCK4972 | 制造商:AGERE 制造商全稱:AGERE 功能描述:Low-Voltage PLL Clock Driver |
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| LCK4993KB-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:Low-Voltage PLL Clock Drivers |
| LCK4993KB-DT | 制造商:AGERE 制造商全稱:AGERE 功能描述:Low-Voltage PLL Clock Drivers |
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