Figure 3-12. sysCONFIG Parallel Port Read Cycle Figure 3-13. sysCONFIG" />
參數(shù)資料
型號: LFEC33E-3FN672C
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 123/163頁
文件大?。?/td> 0K
描述: IC FPGA 32.8KLUTS 672FPBGA
標準包裝: 40
系列: EC
邏輯元件/單元數(shù): 32800
RAM 位總計: 434176
輸入/輸出數(shù): 496
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 672-BBGA
供應(yīng)商設(shè)備封裝: 672-FPBGA(27x27)
3-26
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Figure 3-12. sysCONFIG Parallel Port Read Cycle
Figure 3-13. sysCONFIG Parallel Port Write Cycle
CCLK
1
CS1N
CSN
WRITEN
BUSY
D[0:7]
t
SUCS
t
HCS
t
SUWD
t
CORD
t
DCB
t
HWD
t
BSCYC
t
BSCH
t
BSCL
1. In Master Parallel Mode the FPGA provides CCLK. In Slave Parallel Mode the external device provides CCLK.
Byte 0
Byte 1
Byte 2
Byte n
CCLK
1
CS1N
CSN
WRITEN
BUSY
D[0:7]
t
SUCS
t
HCS
t
SUWD
t
HCBDI
t
DCB
t
HWD
t
BSCYC
t
BSCH
t
BSCL
t
SUCBDI
Byte 0
Byte 1
Byte 2
Byte n
1. In Master Parallel Mode the FPGA provides CCLK. In Slave Parallel Mode the external device provides CCLK.
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