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參數(shù)資料
| 型號： | LFEC33E-3FN672C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 89/163頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 32.8KLUTS 672FPBGA |
| 標準包裝： | 40 |
| 系列： | EC |
| 邏輯元件/單元數(shù)： | 32800 |
| RAM 位總計： | 434176 |
| 輸入/輸出數(shù)： | 496 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 672-BBGA |
| 供應商設備封裝： | 672-FPBGA（27x27） |
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2-28
Architecture
LatticeECP/EC Family Data Sheet
Polarity Control Logic
In a typical DDR Memory interface design, the phase relation between the incoming delayed DQS strobe and the
internal system Clock (during the READ cycle) is unknown.
The LatticeECP/EC family contains dedicated circuits to transfer data between these domains. To prevent setup
and hold violations at the domain transfer between DQS (delayed) and the system Clock a clock polarity selector is
used. This changes the edge on which the data is registered in the synchronizing registers in the input register
block. This requires evaluation at the start of each READ cycle for the correct clock polarity.
Prior to the READ operation in DDR memories DQS is in tristate (pulled by termination). The DDR memory device
drives DQS low at the start of the preamble state. A dedicated circuit detects this transition. This signal is used to
control the polarity of the clock to the synchronizing registers.
sysI/O Buffer
Each I/O is associated with a flexible buffer referred to as a sysI/O buffer. These buffers are arranged around the
periphery of the device in eight groups referred to as Banks. The sysI/O buffers allow users to implement the wide
variety of standards that are found in today’s systems including LVCMOS, SSTL, HSTL, LVDS and LVPECL.
sysI/O Buffer Banks
LatticeECP/EC devices have eight sysI/O buffer banks; each is capable of supporting multiple I/O standards. Each
sysI/O bank has its own I/O supply voltage (VCCIO), and two voltage references VREF1 and VREF2 resources allow-
ing each bank to be completely independent from each other. Figure 2-34 shows the eight banks and their associ-
ated supplies.
In the LatticeECP/EC devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS, PCI and PCI-
X) are powered using VCCIO. LVTTL, LVCMOS33, LVCMOS25 and LVCMOS12 can also be set as fixed threshold
input independent of VCCIO. In addition to the bank VCCIO supplies, the LatticeECP/EC devices have a VCC core logic
power supply, and a VCCAUX supply that power all differential and referenced buffers.
Each bank can support up to two separate VREF voltages, VREF1 and VREF2 that set the threshold for the refer-
enced input buffers. In the LatticeECP/EC devices, some dedicated I/O pins in a bank can be configured to be a
reference voltage supply pin. Each I/O is individually configurable based on the bank’s supply and reference volt-
ages.
相關PDF資料 |
PDF描述 |
|---|---|
| LFECP33E-3FN484C | IC FPGA 32.8KLUTS 360I/O 484-BGA |
| RGM43DTMS | CONN EDGECARD 86POS R/A .156 SLD |
| RMM43DTMS | CONN EDGECARD 86POS R/A .156 SLD |
| RSM43DTMS | CONN EDGECARD 86POS R/A .156 SLD |
| RSM43DTBS | CONN EDGECARD 86POS R/A .156 SLD |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LFEC33E-3FN672I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 32.8K LUTs 1.2V -3 Spd I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFEC33E-3Q208C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC33E-3Q208I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC33E-3QN208C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC33E-3QN208I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
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