參數(shù)資料
型號： LFEC3E-3QN208C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 79/163頁
文件大?。?/td> 0K
描述： IC FPGA 3.1KLUTS 145I/O 208-PQFP
標準包裝： 48
系列： EC
邏輯元件/單元數(shù)： 3100
RAM 位總計： 56320
輸入/輸出數(shù)： 145
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 208-BFQFP
供應(yīng)商設(shè)備封裝： 208-PQFP（28x28）
其它名稱： 220-1774
LFEC3E-3QN208C-ND
2-19
Architecture
LatticeECP/EC Family Data Sheet
Signed and Unsigned with Different Widths
The DSP block supports different widths of signed and unsigned multipliers besides x9, x18 and x36 widths. For
unsigned operands, unused upper data bits should be filled to create a valid x9, x18 or x36 operand. For signed
two’s complement operands, sign extension of the most significant bit should be performed until x9, x18 or x36
width is reached. Table 2-8 provides an example of this.
Table 2-8. An Example of Sign Extension
OVERFLOW Flag from MAC
The sysDSP block provides an overflow output to indicate that the accumulator has overflowed. When two
unsigned numbers are added and the result is a smaller number then accumulator roll over is said to occur and
overflow signal is indicated. When two positive numbers are added with a negative sum and when two negative
numbers are added with a positive sum, then the accumulator “roll-over” is said to have occurred and an overflow
signal is indicated. Note when overflow occurs the overflow flag is present for only one cycle. By counting these
overflow pulses in FPGA logic, larger accumulators can be constructed. The conditions overflow signals for signed
and unsigned operands are listed in Figure 2-23.
Figure 2-23. Accumulator Overflow/Underflow Conditions
Number Unsigned
Unsigned
9-bit
Unsigned
18-bit
Signed
Two’s Complement
Signed 9-Bits
Two’s Complement
Signed 18-bits
+5
0101
000000101
000000000000000101
0101
000000101
000000000000000101
-6
0110
000000110
000000000000000110
1010
111111010
111111111111111010
000000000
000000001
000000010
000000011
111111101
111111110
111111111
Overflow signal is generated
for one cycle when this
boundary is crossed
0
+1
+2
+3
-3
-2
-1
Unsigned Operation
Signed Operation
0101111111
0101111110
0101111101
0101111100
1010000010
1010000001
1010000000
255
254
253
252
254
255
256
000000000
000000001
000000010
000000011
111111101
111111110
111111111
Carry signal is generated for
one cycle when this
boundary is crossed
0
1
2
3
509
510
511
0101111111
0101111110
0101111101
0101111100
1010000010
1010000001
1010000000
255
254
253
252
258
257
256
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LFEC3E-3QN208I 功能描述:FPGA - 現(xiàn)場可編程門陣列 3.1K LUTs 145 IO 1.2 V -3 Spd I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFEC3E-3T100C 功能描述:FPGA - 現(xiàn)場可編程門陣列 3.1K LUTs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFEC3E-3T100CES 功能描述:FPGA - 現(xiàn)場可編程門陣列 3.1 LUT 67 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFEC3E-3T100I 功能描述:FPGA - 現(xiàn)場可編程門陣列 3.1K LUTs 67 IO 1.2V -3 Spd I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFEC3E-3T100IES 功能描述:FPGA - 現(xiàn)場可編程門陣列 3.1 LUT 67 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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