參數(shù)資料
型號： LFEC3E-3TN100C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 81/163頁
文件大小： 0K
描述： IC FPGA 3.1KLUTS 67I/O 100-TQFP
標準包裝： 90
系列： EC
邏輯元件/單元數(shù)： 3100
RAM 位總計： 56320
輸入/輸出數(shù)： 67
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-TQFP（14x14）
2-21
Architecture
LatticeECP/EC Family Data Sheet
For further information about the sysDSP block, please see the list of technical information at the end of this data
sheet.
Programmable I/O Cells (PIC)
Each PIC contains two PIOs connected to their respective sysI/O Buffers which are then connected to the PADs as
shown in Figure 2-24. The PIO Block supplies the output data (DO) and the Tri-state control signal (TO) to sysI/O
buffer, and receives input from the buffer.
Figure 2-24. PIC Diagram
Two adjacent PIOs can be joined to provide a differential I/O pair (labeled as “T” and “C”) as shown in Figure 2-25.
The PAD Labels “T” and “C” distinguish the two PIOs. Only the PIO pairs on the left and right edges of the device
can be configured as LVDS transmit/receive pairs.
One of every 16 PIOs contains a delay element to facilitate the generation of DQS signals. The DQS signal feeds
the DQS bus which spans the set of 16 PIOs. Figure 2-25 shows the assignment of DQS pins in each set of 16
PIOs. The exact DQS pins are shown in a dual function in the Logic Signal Connections table at the end of this data
sheet. Additional detail is provided in the Signal Descriptions table at the end of this data sheet. The DQS signal
from the bus is used to strobe the DDR data from the memory into input register blocks. This interface is designed
for memories that support one DQS strobe per eight bits of data.
PIO B
PADA
"T"
PADB
"C"
OPOS0
ONEG0
OPOS1
ONEG1
TD
INCK
INDD
INFF
IPOS0
IPOS1
CLK
CE
LSR
GSRN
PIO A
sysIO
Buffer
DQS
DDRCLKPOL
IOLD0
IOLT0
D0
DDRCLK
DI
IPOS1
IPOS0
INCK
INDD
INFF
D0
D1
TD
D1
Output
Register Block
(2 Flip Flops)
Tristate
Register Block
(2 Flip Flops)
DDRCLK
Input
Register Block
(5 Flip Flops)
CLKO
CLKI
CEO
CEI
Control
Muxes
LSR
GSR
相關(guān)PDF資料
PDF描述
LFEC1E-5TN144C IC FPGA 1.5KLUTS 97I/O 144-TQFP
HCC65DRTF CONN EDGECARD 130PS DIP .100 SLD
FMC15DRYS CONN EDGECARD 30POS DIP .100 SLD
IR2166 IC PFC/BALLAST CONTROL 16-DIP
LFEC1E-3QN208I IC FPGA 1.5KLUTS 208PQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LFEC3E-3TN100I 功能描述:FPGA - 現(xiàn)場可編程門陣列 3.1K LUTs 67 IO 1.2V -3 Spd I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
LFEC3E-3TN144C 功能描述:FPGA - 現(xiàn)場可編程門陣列 3.1K LUTs Pb-Free RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
LFEC3E-3TN144I 功能描述:FPGA - 現(xiàn)場可編程門陣列 3.1K LUTs 97 IO 1.2V -3 Spd I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
LFEC3E-4F256C 功能描述:FPGA - 現(xiàn)場可編程門陣列 3.1K LUTs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
LFEC3E-4F256CES 功能描述:FPGA - 現(xiàn)場可編程門陣列 3.1 LUT 160 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*