參數(shù)資料
型號(hào)： LFEC3E-4TN100C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 74/163頁
文件大小： 0K
描述： IC FPGA 3.1KLUTS 100TQFP
標(biāo)準(zhǔn)包裝： 90
系列： EC
邏輯元件/單元數(shù)： 3100
RAM 位總計(jì)： 56320
輸入/輸出數(shù)： 67
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-TQFP（14x14）
2-15
Architecture
LatticeECP/EC Family Data Sheet
decoders. These complex signal processing functions use similar building blocks such as multiply-adders and mul-
tiply-accumulators.
sysDSP Block Approach Compared to General DSP
Conventional general-purpose DSP chips typically contain one to four (Multiply and Accumulate) MAC units with
fixed data-width multipliers; this leads to limited parallelism and limited throughput. Their throughput is increased by
higher clock speeds. The LatticeECP, on the other hand, has many DSP blocks that support different data-widths.
This allows the designer to use highly parallel implementations of DSP functions. The designer can optimize the
DSP performance vs. area by choosing an appropriate level of parallelism. Figure 2-18 compares the serial and the
parallel implementations.
Figure 2-18. Comparison of General DSP and LatticeECP-DSP Approaches
sysDSP Block Capabilities
The sysDSP block in the LatticeECP-DSP family supports four functional elements in three 9, 18 and 36 data path
widths. The user selects a function element for a DSP block and then selects the width and type (signed/unsigned)
of its operands. The operands in the LatticeECP-DSP family sysDSP Blocks can be either signed or unsigned but
not mixed within a function element. Similarly, the operand widths cannot be mixed within a block.
The resources in each sysDSP block can be configured to support the following four elements:
MULT
(Multiply)
MAC
(Multiply, Accumulate)
MULTADD
(Multiply, Addition/Subtraction)
MULTADDSUM (Multiply, Addition/Subtraction, Accumulate)
The number of elements available in each block depends on the width selected from the three available options x9,
x18, and x36. A number of these elements are concatenated for highly parallel implementations of DSP functions.
Table 2-1 shows the capabilities of the block.
Multiplier 0
Operand
A
Operand
B
Operand
A
Operand
B
Operand
A
Operand
B
Multiplier 1
Multiplier
(k-1)
Accumulator
Output
m/k
loops
Single
Multiplier
x
xx
x
Operand
A
Accumulator
Operand
B
M loops
Function implemented in
General purpose DSP
Function implemented
in LatticeECP
Σ
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參數(shù)描述
LFEC3E-4TN100I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 3.1K LUTs 67 IO 1.2V -4 Spd I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFEC3E-4TN144C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 3.1K LUTs Pb-Free RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFEC3E-4TN144I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 3.1K LUTs 97 IO 1.2V -4 Spd I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFEC3E-5F256C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 3.1K LUTs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFEC3E-5F256CES 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 3.1 LUT 160 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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