Figure 2-4. Slice Diagram Table 2-1. Slice Signal Descriptions Function Type Signal Nam" />
參數(shù)資料
型號: LFECP33E-4FN672I
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 131/163頁
文件大?。?/td> 0K
描述: IC FPGA 32.8KLUTS 672FPBGA
產(chǎn)品培訓(xùn)模塊: LatticeECP3 Introduction
標(biāo)準(zhǔn)包裝: 40
系列: ECP
邏輯元件/單元數(shù): 32800
RAM 位總計(jì): 434176
輸入/輸出數(shù): 496
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 672-BBGA
供應(yīng)商設(shè)備封裝: 672-FPBGA(27x27)
2-4
Architecture
LatticeECP/EC Family Data Sheet
Figure 2-4. Slice Diagram
Table 2-1. Slice Signal Descriptions
Function
Type
Signal Names
Description
Input
Data signal
A0, B0, C0, D0 Inputs to LUT4
Input
Data signal
A1, B1, C1, D1 Inputs to LUT4
Input
Multi-purpose
M0
Multipurpose Input
Input
Multi-purpose
M1
Multipurpose Input
Input
Control signal
CE
Clock Enable
Input
Control signal
LSR
Local Set/Reset
Input
Control signal
CLK
System Clock
Input
Inter-PFU signal
FCIN
Fast Carry In
1
Output
Data signals
F0, F1
LUT4 output register bypass signals
Output
Data signals
Q0, Q1
Register Outputs
Output
Data signals
OFX0
Output of a LUT5 MUX
Output
Data signals
OFX1
Output of a LUT6, LUT7, LUT8
2 MUX depending on the slice
Output
Inter-PFU signal
FCO
For the right most PFU the fast carry chain output
1
1. See Figure 2-3 for connection details.
2. Requires two PFUs.
LUT4 &
CARRY
LUT4 &
CARRY
Slice
A0
B0
C0
D0
FF/
Latch
OFX0
F0
Q0
A1
B1
C1
D1
CI
CO
F
SUM
CE
CLK
LSR
FF/
Latch
OFX1
F1
Q1
F
SUM
D
M1
To / From
Different slice / PFU
To / From
Different slice / PFU
LUT
Expansion
Mux
M0
OFX0
From
Routing
To
Routing
Control Signals
selected and
inverted per
slice in routing
Interslice signals
are not shown
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