Table 2-14. Supported Output Standards Hot Socketing The LatticeECP/EC devices have been care" />
參數(shù)資料
型號： LFECP33E-4FN672I
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 92/163頁
文件大?。?/td> 0K
描述： IC FPGA 32.8KLUTS 672FPBGA
產(chǎn)品培訓(xùn)模塊： LatticeECP3 Introduction
標(biāo)準(zhǔn)包裝： 40
系列： ECP
邏輯元件/單元數(shù)： 32800
RAM 位總計： 434176
輸入/輸出數(shù)： 496
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 672-BBGA
供應(yīng)商設(shè)備封裝： 672-FPBGA（27x27）
2-31
Architecture
LatticeECP/EC Family Data Sheet
Table 2-14. Supported Output Standards
Hot Socketing
The LatticeECP/EC devices have been carefully designed to ensure predictable behavior during power-up and
power-down. Power supplies can be sequenced in any order. During power up and power-down sequences, the
I/Os remain in tristate until the power supply voltage is high enough to ensure reliable operation. In addition,
leakage into I/O pins is controlled within specified limits, this allows for easy integration with the rest of the sys-
tem. These capabilities make the LatticeECP/EC ideal for many multiple power supply and hot-swap applica-
tions.
Configuration and Testing
The following section describes the configuration and testing features of the LatticeECP/EC devices.
IEEE 1149.1-Compliant Boundary Scan Testability
All LatticeECP/EC devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant test
access port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a
serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to
Output Standard
Drive
VCCIO (Nom.)
Single-ended Interfaces
LVTTL
4mA, 8mA, 12mA, 16mA, 20mA
3.3
LVCMOS33
4mA, 8mA, 12mA 16mA, 20mA
3.3
LVCMOS25
4mA, 8mA, 12mA, 16mA, 20mA
2.5
LVCMOS18
4mA, 8mA, 12mA, 16mA
1.8
LVCMOS15
4mA, 8mA
1.5
LVCMOS12
2mA, 6mA
1.2
LVCMOS33, Open Drain
4mA, 8mA, 12mA 16mA, 20mA
—
LVCMOS25, Open Drain
4mA, 8mA, 12mA 16mA, 20mA
—
LVCMOS18, Open Drain
4mA, 8mA, 12mA 16mA
—
LVCMOS15, Open Drain
4mA, 8mA
—
LVCMOS12, Open Drain
2mA, 6mA
—
PCI33
N/A
3.3
HSTL18 Class I, II, III
N/A
1.8
HSTL15 Class I, III
N/A
1.5
SSTL3 Class I, II
N/A
3.3
SSTL2 Class I, II
N/A
2.5
SSTL18 Class I
N/A
1.8
Differential Interfaces
Differential SSTL3, Class I, II
N/A
3.3
Differential SSTL2, Class I, II
N/A
2.5
Differential SSTL18, Class I
N/A
1.8
Differential HSTL18, Class I, II, III
N/A
1.8
Differential HSTL15, Class I, III
N/A
1.5
LVDS
N/A
2.5
BLVDS
1
N/A
2.5
LVPECL
1
N/A
3.3
RSDS
1
N/A
2.5
1. Emulated with external resistors.
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