- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄4564 > LFX200B-04F256C (Lattice Semiconductor Corporation)IC FPGA 200K GATES 256-BGA PDF資料下載
參數(shù)資料
| 型號(hào)： | LFX200B-04F256C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁(yè)數(shù)： | 28/119頁(yè) |
| 文件大小： | 0K |
| 描述： | IC FPGA 200K GATES 256-BGA |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | ispXPGA® |
| 邏輯元件/單元數(shù)： | 2704 |
| RAM 位總計(jì)： | 113664 |
| 輸入/輸出數(shù)： | 160 |
| 門(mén)數(shù)： | 210000 |
| 電源電壓： | 2.3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 256-BGA |
| 供應(yīng)商設(shè)備封裝： | 256-FPBGA（17x17） |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)當(dāng)前第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)
Lattice Semiconductor
ispXPGA Family Data Sheet
12
Memory
The ispXPGA architecture provides a large amount of resources for memory intensive applications. Embedded
Block RAMs (EBRs) are available to complement the Distributed Memory that is configured in the PFUs (see Look-
Up Table -Distributed Memory Mode in the PFU section above). Each memory element can be configured as RAM
or ROM. Additionally, the internal logic of the device can be used to configure the memory elements as FIFO and
other storage types. These EBRs are referred to as sysMEM blocks. Refer to Table 1 for memory resources per
device.
sysMEM Blocks
The sysMEM blocks are organized in columns distributed throughout the device. Each EBR contains 4.6K bits of
dual-port RAM with dedicated control, address, and data lines for each port. Each column of sysMEM blocks has
dedicated address and control lines that can be used by each block separately or cascaded to form larger memory
elements. The memory cells are symmetrical and contain two sets of identical control signals. Each port has a
read/write clock, clock enable, write enable, and output enable. Figure 12 illustrates the sysMEM block.
The ispXPGA memory block can operate as single-port or dual-port RAM. Supported configurations are:
512 x 9 bits single-port
(8 bits data / 1 bit parity)
256 x 18 bits single-port
(16 bits data / 2 bits parity)
512 x 9 bits dual-port
(8 bits data / 1 bit parity)
256 x18 bits dual-port
(16 bits data / 2 bits parity)
The data widths of “9” and “18” are ideal for applications where parity is necessary. This allows 9 data bits, 8 data
bits plus a parity bit, 18 data bits, or 16 data bits plus two parity bits. The logic for generating and checking the par-
ity must be customized separately.
Figure 12. sysMEM Block Diagram
Read and Write Operations
The ispXPGA EBR has fully synchronous read and write operations as well as an asynchronous read operation.
These operations allow several different types of memory to be implemented in the device.
Synchronous Read: The Clock Enable (CE) and Write Enable (WE) signals control the synchronous read opera-
tion. When the CE signal is low, the clock is enabled. When the WE signal is low the read operation begins. Once
the address (ADDR) is present, a rising clock edge (or falling edge depending on polarity) causes the stored data
to be available on the DATA port. Figure 13 illustrates the synchronous read timing.
sysMEM Block
ADDRA
DATAA
WEA
OEA
CLKA
CEA
ADDRB
DATAB
WEB
OEB
CLKB
CE B
SELECT
DEVICES
DISCONTINUED
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LFX200B-04FN256C | IC FPGA 210KGATES 256FPBGA |
| RF803E | IC ENCODER 3 DGTL I/O 8-PDIP |
| DS9100-B+ | CONTACT TOUCH AND HOLD |
| LFEC33E-4FN484I | IC FPGA 32.8KLUTS 484FPBGA |
| LFEC33E-5FN484C | IC FPGA 32.8KLUTS 484FPBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LFX200B-04F516C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 210K 208 I/O ispJTAG RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFX200B-04FH516C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 Use LFX200B-04F516C RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFX200B-04FN256C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 210K Gt ispJTAG 2.5/ 3.3V -4 Spd RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFX200B-04FN516C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 210K Gt ispJTAG 2.5 /3.3V -4 Spd RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFX200B-04FN516C1 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。