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參數(shù)資料
| 型號(hào)： | LH521028 |
| 廠商： | Sharp Corporation |
| 英文描述： | CMOS 64K x 18 Static RAM |
| 中文描述： | 64K的× 18的CMOS靜態(tài)RAM |
| 文件頁數(shù)： | 13/15頁 |
| 文件大?。?/td> | 153K |
| 代理商： | LH521028 |
BYTE OPERATIONS
Byte Read Description (Figure 12)
To read individual bytes, the device must be enabled
(E is LOW), W must be HIGH, the outputs must be
enabled (G is LOW) and the addresses must be either
stable or latched with ALE. Figure 12 is one example of
the byte read capabilities of this device. The example
shows two read operations. The first is a read of the high
byte of the current memory location and the second is a
read of the low byte of the memory location.
(1) At the beginning of the cycle both S
L
and S
H
are
HIGH.
(2) S
H
goes LOW initiating a Read on the upper byte
DQ
H(9-17)
. S
L
remains HIGH keeping the lower byte
DQ
L(0-8)
disabled and in a high-impedance mode.
(3) S
L
goes LOW activating DQ
L(0-8)
.Valid data is avail-
able in t
SA
following S
L
going LOW.
(4) When S
H
goes HIGH
,
DQ
H(9-17)
remains valid for t
SHZ
before returning to a high-impedance condition.
(5) Finally, the Read for the lower byte is terminated by
deasserting S
L
(HIGH). DQ
L(0-8)
remains active for
t
SHZ
following S
L
going HIGH.
ADDRESS
VALID DATA
VALID DATA
ALE
G
S
L
S
H
DQ
L (0-8)
DQ
H (9-17)
(1)(2)
(3)
(4)
(5)
521028-10
VALID ADDRESS
Figure 12. Byte Read (E is LOW and W is HIGH)
CMOS 64K
×
18 Static RAM
LH521028
4-223
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LH521028A | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:CMOS 64K x 18 Static RAM |
| LH521028AU-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 SRAM |
| LH521028AU-17 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 SRAM |
| LH521028AU-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 SRAM |
| LH521028AU-25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 SRAM |
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