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參數(shù)資料
| 型號： | LH521028 |
| 廠商： | Sharp Corporation |
| 英文描述： | CMOS 64K x 18 Static RAM |
| 中文描述： | 64K的× 18的CMOS靜態(tài)RAM |
| 文件頁數(shù)： | 9/15頁 |
| 文件大?。?/td> | 153K |
| 代理商： | LH521028 |
TIMING DIAGRAMS – READ CYCLE (cont’d)
Read Cycle No. 3 (Latched Address Controlled
Read)
Chip is in Read Mode: W is HIGH, E, S
H
, S
L
and G are
LOW. Both t
AA
and t
LEA
must be met before valid data is
available. If the address is valid prior to the rising edge of
ALE, then the access time is t
LEA
. If the address is valid
after ALE is HIGH (or if ALE is tied HIGH) then the access
time is t
AA
. Crosshatched portion of Data Out implies that
data lines are in the Low-Z state but the data is not
guaranteed to be valid until t
AA
.
ADDRESS
DQ
t
ASL
521028-4
E, S
H
, S
L
VALID ADDRESS
PREVIOUS DATA
VALID DATA
t
LHM
t
AA
t
LEA
t
AHL
t
LH
ALE
Figure 6. Read Cycle No. 3
CMOS 64K
×
18 Static RAM
LH521028
4-219
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LH521028A | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:CMOS 64K x 18 Static RAM |
| LH521028AU-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 SRAM |
| LH521028AU-17 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 SRAM |
| LH521028AU-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 SRAM |
| LH521028AU-25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 SRAM |
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