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參數(shù)資料
| 型號： | LH5P1632 |
| 廠商： | Sharp Corporation |
| 英文描述： | CMOS 512K (32K x 16) Pseudo-Static RAM |
| 中文描述： | 為512k的CMOS（32K的× 16），偽靜態(tài)存儲器 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 89K |
| 代理商： | LH5P1632 |
AC CHARACTERISTICS
1, 2, 3
(T
A
= 0 to +70
°
C, V
CC
= 5.0 V
±
10%)
PARAMETER
SYMBOL
–80 ns
–150 ns
UNIT
NOTE
MIN.
MAX.
MIN.
MAX.
READ OR WRITE CYCLE
t
RC
140
t
RMW
205
t
CE
80
t
P
50
t
AS
0
t
AH
20
t
RCS
0
t
RCH
0
t
CEA
t
OEA
t
CLZ
10
t
OLZ
0
t
OSW
0
t
CHZ
0
t
OHZ
0
t
WHZ
0
t
OES
10
t
OEH
0
t
OEL
10
t
WCP
60
t
WCS
60
t
WCH
60
t
DSW
30
t
DSC
30
t
DHW
0
t
DHC
0
t
T
3
t
REF
REFRESH CYCLE
t
FC
140
t
RFD
50
t
FAP
30
Random read, write cycle time
Read modify write cycle time
CE pulse width
CE precharge time
Address setup time
Address hold time
Read command setup time
Read command hold time
CE access time
OE access time
CE to output in Low-Z
OE to output in Low-Z
OE setup time for WR
Output disable time from CE
Output disable time from OE
Output disable time from WR
OE setup time
OE hold time
OE lead time
Write command pulse width
Write command setup time
Write command hold time
Data setup time from WR
Data setup time from CE
Data hold time from WR
Data hold time from CE
Transition time (rise and fall)
Refresh time interval
210
280
150
60
0
30
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
10,000
10,000
4
4
80
30
150
70
5
5
10
0
0
0
0
0
10
0
10
85
85
85
50
50
0
0
3
25
25
25
35
35
35
35
4
35
4
Auto refresh cycle time
Refresh delay time from CE
Refresh pulse width (Auto Refresh)
Refresh precharge time (Auto
Refresh)
CE delay time from Refresh active
(Auto Refresh)
190
60
80
ns
ns
ns
8,000
8,000
t
FP
40
30
ns
t
FCE
160
225
ns
NOTES:
1.
In order to initialize the circuit, CE and OEL/RFSH should be kept
V
IH
for 200
μ
s after power on and followed by at least 8 dummy
cycles.
2.
AC characteristics shall be tested with t
T
= 5 ns.
3.
AC characteristics are measured at the following condition (see figure
at right).
4.
Address is latched at the negative edge of CE.
5.
Measured with a load equivalent to 2TTL + 100 pF.
6.
Data for the lower byte (I/O
to I/O
) is latched at the positive edge
of LWR or the positive edge of CE. Data for the upper byte (I/O
to
I/O
16
) is latched at the positive edge of UWR or the positive edge
of CE.
2.4 V
0.8 V
2.6 V
0.6 V
2.2 V
0.8 V
OUTPUT
INPUT
5P1632-9
Figure 3. AC Characteristics
LH5P1632
CMOS 512K (32K
×
16) Pseudo-Static RAM
4
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| LH5P1632D-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 Pseudo-Static RAM |
| LH5P1632D-80 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 Pseudo-Static RAM |
| LH5P1632N-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 Pseudo-Static RAM |
| LH5P1632N-80 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 Pseudo-Static RAM |
| LH5P8128 | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:CMOS 1M (128K x 8) Pseudo-Static RAM |
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