參數(shù)資料
型號(hào)： LH7A400N0B000
廠商： Sharp Corporation
英文描述： 32-Bit System-on-Chip
中文描述： 32位系統(tǒng)級(jí)芯片
文件頁數(shù)： 11/53頁
文件大?。?/td> 446K
代理商： LH7A400N0B000
32-Bit System-on-Chip
LH7A400
Preliminary Data Sheet
12/8/03
11
NOTES:
*Signals beginning with ‘n’ are Active LOW.
J7
G3
UARTRX2
UART2 Receive Data Input. This pin is an output
for JTAG boundary scan only.
Synchronous Serial Port Clock
Synchronous Serial Port Receive
Synchronous Serial Port Transmit
Input
Input
H4
J1
J2
J3
J6
J7
SSPCLK
SSPRX
SSPTX
SSPFRM/
nSSPFRM
COL0
COL1
COL2
COL3
COL4
COL5
COL6
COL7
TBUZ
LOW
Input
LOW
Input:
nSSPFRM
LOW
Input
LOW
8 mA
8 mA
J3
J2
Synchronous Serial Port Frame Sync
Input
8 mA
F6
F5
G1
G2
G4
G5
H1
H2
H3
G2
G1
H3
H5
H6
H7
H2
H1
J1
Keyboard Interface
HIGH
HIGH
8 mA
Timer Buzzer (254 kHz MAX.)
Boot Device Media Change. Used with the
WIDTH0 and WIDTH1 pins to specify boot mem-
ory device.
External Memory Width Pins. Also, used with
Battery OK
Battery Change
JTAG Data In. This signal is internally pulled-up
to VDD.
JTAG Clock. This signal should be externally
pulled-up to VDD.
JTAG Data Out. This signal should be externally
pulled up to VDD with a 33 k
resistor.
JTAG Test Mode select. This signal is internally
pulled-up to VDD.
Test Pin 0. Internally pulled up to VDD. For Normal
mode, leave open. For JTAG mode, tie to GND.
See Table 2.
Test Pin 1. internally pulled up to VDD. For Normal
and JTAG mode, leave open. See Table 2.
LOW
LOW
8 mA
C3
F5
MEDCHG
Input (Schmitt) Input
P11
R12
D1
D2
T14
T15
E3
F6
WIDTH0
WIDTH1
BATOK
nBATCHG
Input (Schmitt) Input
Input (Schmitt) Input
Input with
Pull-up
A1
E5
TDI
Input with
Pull-up
B1
C2
TCK
Input
Input
B2
D3
TDO
Input
No Change
4 mA
C1
C1
TMS
Input with
Pull-up
Input with
Pull-up
T12
P15
nTEST0
Input with
Pull-up
Input with
Pull-up
R15
P13
nTEST1
Input with
Pull-up
Input with
Pull-up
Table 1. Functional Pin List (Cont’d)
PBGA
PIN
CABGA
PIN
SIGNAL
DESCRIPTION
RESET
STATE
STANDBY
STATE
OUTPUT
DRIVE
Table 2. nTest Pin Function
MODE
JTAG
Normal
nTEST0
0
1
nTEST1
1
1
nURESET
1
x
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