參數(shù)資料
型號: LH7A400N0B000
廠商: Sharp Corporation
英文描述: 32-Bit System-on-Chip
中文描述: 32位系統(tǒng)級芯片
文件頁數(shù): 40/53頁
文件大?。?/td> 446K
代理商: LH7A400N0B000
LH7A400
32-Bit System-on-Chip
40
12/8/03
Preliminary Data Sheet
SMC Waveforms
Figure 7 shows the waveform and timing for an
External Asynchronous Memory Write. Note that the
deassertion of nWE can preceed the deassertion of
nCS by a maximum of one HCLK, or at minimum, can
coincide (see Table 9). Figure 8 shows the waveform
and timing for an External Asynchronous Memory
Read, with one Wait State.
Figure 7. External Asynchronous Memory Write
Figure 8. External Asynchronous Memory Read
HCLK
(See Note 2)
ADDRESS
DATA
A[27:0]
(See Note 1)
D[31:0]
nCSx, CSx
nWE[3:0]
t
OVD
t
OHD
t
OVCSW
t
OHCS
t
OVWE
t
OHWE
t
OHWECS
LH7A400-20
NOTES:
1. A[24:0] when SCI used.
2. HCLK is an internal signal, shown for reference only.
0
1
2
3
4
HCLK
(See Note)
ADDRESS
DATA
A[25:0]
D[31:0]
nCSx, CSx
nOE
t
ISD
t
IHD
t
OHCS
t
OVCSR
t
OVOE
t
OHOE
LH7A400-21
NOTE:
HCLK is an internal signal, shown for reference only.
0
1
2
3
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