32-Bit System-on-Chip
LH7A400
Preliminary Data Sheet
12/8/03
49
Printed Circuit Board Layout Practices
LH7A400 POWER SUPPLY DECOUPLING
The LH7A400 has separate power and ground pins
for different internal circuitry sections. The VDD and
VSS pins supply power to I/O buffers, while VDDC and
VSSC supply power to the core logic, and VDDA/VSSA
supply analog power to the PLLs.
Each of the VDD and VDDC pins must be provided
with a low impedance path to the corresponding board
power supply. Likewise, the VSS and VSSC pins must
be provided with a low impedance path to the board
ground.
Each power supply must be decoupled to ground
using at least one 0.1
μ
F high frequency capacitor
located as close as possible to a VDDx, VSSx pin pair
on each of the four sides of the chip. If room on the cir-
cuit board allows, add one 0.01
μ
F high frequency
capacitor near each VDDx, VSSx pair on the chip.
To be effective, the capacitor leads and associated
circuit board traces connecting to the chip VDDx, VSSx
pins must be kept to less than half an inch (12.7 mm)
per capacitor lead. There must be one bulk 10
μ
F
capacitor for each power supply placed near one side
of the chip.
REQUIRED LH7A400 PLL, VDDA, VSSA FILTER
The VDDA pins supplies power to the chip PLL cir-
cuitry. VSSA is the ground return path for the PLL cir-
cuit. These pins must have a low-pass filter attached as
shown in Figure 23.
The Schottky diode shown in the schematic must
have a low forward drop specification to allow VDDA to
quickly transition through the entire input voltage range.
The power pin VDDA path must be a single wire
from the IC package pin to the high frequency capaci-
tor, then to the low frequency capacitor, and finally
through the series resistor to the board power supply.
The distance from the IC pin to the high frequency
capacitor must be kept as short as possible.
Similarly, the VSSA path is from the IC pin to the
high frequency capacitor, then to the low frequency
capacitor, keeping the distance from the IC pin to the
high frequency cap as short as possible.
UNUSED INPUT SIGNAL CONDITIONING
Floating input signals can cause excessive power
consumption. Unused inputs without internal pull-up or
pull-down resistors should be pulled up or down exter-
nally, to tie the signal to its inactive state.
Some GPIO signals may default to inputs. If the pins
that carry these signals are unused, software can pro-
gram these signals as outputs, eliminating the need for
pull-ups or pull-downs. Power consumption may be
higher than expected until software completes pro-
gramming the GPIO. Some LH7A400 inputs have inter-
nal pull-ups or pull-downs. If unused, these inputs do
not require external conditioning.
OTHER CIRCUIT BOARD LAYOUT PRACTICES
All outputs have fast rise and fall times. Printed cir-
cuit trace interconnection length must therefore be
reduced to minimize overshoot, undershoot and reflec-
tions caused by transmission line effects of these fast
output switching times. This recommendation particu-
larly applies to the address and data buses.
When considering capacitance, calculations must
consider all device loads and capacitances due to the
circuit board traces. Capacitance due to the traces will
depend upon a number of factors, including the trace
width, dielectric material the circuit board is made from
and proximity to ground and power planes.
Attention to power supply decoupling and printed cir-
cuit board layout becomes more critical in systems with
higher capacitive loads. As these capacitive loads
increase, transient currents in the power supply and
ground return paths also increase.
Note that the VSSA pin specifically does not have a connec-
tion to the circuit board ground. The LH7A400 PLL circuit has
an internal DC ground connection to VSS (GND), so the ex-
ternal VSSA pin must NOT be connected to the circuit board
ground, but only to the filter components.
CAUTION
Figure 23. VDDA, VSSA Filter Circuit
LH7A400-189
VDDA
VDDC
VSSA
22 μF
100
VDDC
(SOURCE)
0.1 μF
+
LH7A400