參數(shù)資料
型號: LIS3LV02DL
廠商: STMICROELECTRONICS
元件分類: 模擬信號調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, PBGA16
封裝: 4.40 X 7.50 MM, 1 MM HEIGHT, GREEN, PLASTIC, LGA-16
文件頁數(shù): 7/48頁
文件大?。?/td> 681K
代理商: LIS3LV02DL
LIS3LV02DL
Mechanical and electrical specifications
15/48
2.3
Communication interface characteristics
2.3.1
SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top.
Figure 3.
SPI slave timing diagram (2)
2.
Measurement points are done at 0.2Vdd_IO and 0.8Vdd_IO, for both input and output port
3.
When no communication is on-going, data on CS, SPC, SDI and SDO are driven by internal pull-up
resistors
Table 6.
SPI Slave Timing Values
Symbol
Parameter
Value(1)
1.
Values are guaranteed at 8 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization
results, not tested in production
Unit
Min
Max
tc(SPC)
SPI clock cycle
125
ns
fc(SPC)
SPI clock frequency
8
MHz
tsu(CS)
CS setup time
5
ns
th(CS)
CS hold time
10
tsu(SI)
SDI input setup time
5
th(SI)
SDI input hold time
15
tv(SO)
SDO valid output time
55
th(SO)
SDO output hold time
7
tdis(SO)
SDO output disable time
50
SPC
CS
SDI
SDO
tsu(CS)
tv(SO)
th(SO)
th(SI)
tsu(SI)
th(CS)
tdis(SO)
tc(SPC)
MSB IN
MSB OUT
LSB OUT
LSB IN
(3)
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