參數(shù)資料
型號(hào)： LM12434CIWM
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 模擬信號(hào)調(diào)理
英文描述： Sign Data Acquisition System with Serial I/O and Self-Calibration
中文描述： SPECIALTY ANALOG CIRCUIT, PDSO28
封裝： SOP-28
文件頁(yè)數(shù)： 11/80頁(yè)
文件大?。?/td> 1561K
代理商： LM12434CIWM
2.0 Electrical Specifications
(Continued)
2.3 DIGITAL SWITCHING CHARACTERISTICS
The following specifications apply to the LM12434 and LM12
à
L
ó
438 for V
A
a
e
V
D
a e
5V
à
3.3V
ó
, AGND
e
DGND
e
0V, C
L
(load capacitance) on output lines
e
80 pF unless otherwise specified.
Boldface limits apply for T
A
e
T
J
e
T
MIN
to T
MAX
,
all other limits for T
A
e
T
J
e
25
§
C. (Notes 6, 7, and 9) (Continued)
2.3.2 8051 Interface Mode
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 11)
Units
(Limit)
(SeeFigure Below)
t
9
TXD (Serial Clock Period)
125
à
250
ó
ns (min)
t
10
CS Set-Up Time to First
Clock Transition
25
à
40
ó
ns (min)
t
11
Data in Valid Set-Up Time to
TXD Clock High
40
ns (min)
t
12
Data in Valid Hold Time
from TXD Clock High
40
à
90
ó
ns (min)
t
13
Data Out Hold Time
from TXD Clock High
70
à
120
ó
ns (max)
t
14
CS Hold Time from Last TXD
High in a Read or Write Cycle
(Excluding Burst Read Cycle)
25
à
50
ó
ns (min)
t
15
CS Inactive to CS Active Again
3
CLK Cycle
(min)
*
t
16
SCLK Idle Time between the
End of the Command Byte
Transfer and the Start of the
Data Transfer in Read Cycles
3
CLK Cycle
(min)
*
*
CLK is the main clock input to the device, pin number 24 in PLCC package or pin number 2 in SO package.
TL/H/11879–21
11
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