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參數(shù)資料
| 型號： | LM12434CIWM |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號調理 |
| 英文描述： | Sign Data Acquisition System with Serial I/O and Self-Calibration |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO28 |
| 封裝： | SOP-28 |
| 文件頁數(shù)： | 34/80頁 |
| 文件大?。?/td> | 1561K |
| 代理商： | LM12434CIWM |
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6.0 Operational Information
(Continued)
Bits 12–15
store the user-programmable acquisition time.
The Sequencer keeps the internal S/H in the acquisition
mode for a fixed number of clock cycles (nine clock cycles,
for 12-bit
a
sign conversions and two clock cycles for 8-bit
a
sign conversions or ‘‘watchdog’’ comparisons) plus a
variable number of clock cycles equal to twice the value
stored in Bits 12–15. Thus, the S/H’s acquisition time is (9
a
2D) clock cycles for 12-bit
a
sign conversions and (2
a
2D) clock cycles for 8-bit
a
sign conversions or ‘‘watch-
dog’’ comparisons, where D is the value stored in Bits 12–
15. The minimum acquisition time compensates for the typi-
cal internal multiplexer series resistance of 2 k
X
, and any
additional delay created by Bits 12–15 compensates for
source resistances greater than 60
X
à
80
X
ó
. The necessary
acquisition time is determined by the source impedance at
the multiplexer input. If the source resistance R
S
k
60
X
and the clock frequency is 8 MHz, the value stored in bits
12–15 (D) can be 0000. If R
S
l
60
X
, the following equa-
tions determine the value that should be stored in
bits 12–15.
D
e
0.45 x R
S
x f
CLK
for 12-bits
a
sign
D
e
0.36 x R
S
x f
CLK
for 8-bits
a
sign and ‘‘watchdog’’
R
S
is in k
X
and f
CLK
is in MHz. Round the result to the next
higher integer value. If the value of 0 obtained from the
expressions above is greater than 15, it is advisable to lower
the source impedance by using an analog buffer between
the signal source and the LM12
à
L
ó
438’s multiplexer inputs.
The value of D can also be used to compensate for the
settling or response time of external processing circuits con-
nected between the LM12434’s MUXOUT and S/H IN pins.
Instruction RAM, Bank 2 RP
e
01
The second Instruction RAM section is selected by placing
‘‘01’’ in Bits 8 and 9 of the Configuration register.
Bits 0–7
hold ‘‘watchdog’’
limit
Y
1
. When Bit 11 of Instruc-
tion RAM ‘‘00’’ is set to a ‘‘1’’, the LM12434 and
LM12
à
L
ó
438 performs a ‘‘watchdog’’ comparison of the
sampled analog input signal with the limit
Y
1 value first,
followed by a comparison of the same sampled analog input
signal with the value found in limit
Y
2 (Instruction RAM
‘‘10’’).
Bit 8
holds limit
Y
1’s sign.
Bit 9
’s state determines the limit condition that generates a
‘‘watchdog’’ interrupt. A ‘‘1’’ causes a voltage greater than
limit
Y
1 to generate an interrupt, while a ‘‘0’’ causes a volt-
age less than limit
Y
1 to generate an interrupt.
Bits 10–15
are not used.
Instruction RAM, Bank 3, RP
e
10
The third Instruction RAM section is selected by placing
‘‘10’’ in Bits 8 and 9 of the Configuration register.
Bits 0–7
hold ‘‘watchdog’’
limit
Y
2
. When Bit 11 of Instruc-
tion RAM ‘‘00’’ is set to a ‘‘1’’, the LM12434 and
LM12
à
L
ó
438 performs a ‘‘watchdog’’ comparison of the
sampled analog input signal with the limit
Y
1 value first (In-
struction RAM ‘‘01’’), followed by a comparison of the same
sampled analog input signal with the value found in limit
Y
2.
Bit 8
holds limit
Y
2’s sign.
Bit 9
’s state determines the limit condition that generates a
‘‘watchdog’’ interrupt. A ‘‘1’’ causes a voltage greater than
limit
Y
2 to generate an interrupt, while a ‘‘0’’ causes a volt-
age less than limit
Y
2 to generate an interrupt.
Bits 10–15
are not used.
TABLE III. LM12
à
L
ó
438 Operating Mode Input Channel Selection through Input Multiplexer
Normal Operating Mode
Non-Inverting Input
Channel Selection Bits
in Instruction Register
D4, D3, D2
Input Channel to Be
Connected to A/D
Non-Inverting Input
(IN
a
)
Inverting Input
Channel Selection Bits
in Instruction Register
D7, D6, D5
Input Channel to Be
Connected to A/D
Inverting Input
(IN
b
)
000
IN0
000
GND
001
IN1
001
IN1
010
IN2
010
IN2
011
IN3
011
IN3
100
IN4
100
IN4
101
IN5
101
IN5
110
IN6
110
IN6
111
IN7
111
IN7
34
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