- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄358809 > LM12434CIWM (NATIONAL SEMICONDUCTOR CORP) Sign Data Acquisition System with Serial I/O and Self-Calibration PDF資料下載
參數(shù)資料
| 型號(hào)： | LM12434CIWM |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | Sign Data Acquisition System with Serial I/O and Self-Calibration |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO28 |
| 封裝： | SOP-28 |
| 文件頁數(shù)： | 56/80頁 |
| 文件大?。?/td> | 1561K |
| 代理商： | LM12434CIWM |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁當(dāng)前第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁
7.0 Digital Interface
(Continued)
Burst read cycle:
A burst read cycle starts the same way
as a single read cycle, but the B bit in the command byte is
set to one, indicating a burst read cycle. Following the com-
mand byte the data is output on the RXD line as long as the
DAS receives TXD clock from the system. To tell the DAS
when a burst read cycle is completed, CS should be set high
after the 8th and before the 15th SCLK cycle during the last
data byte transfer (seeFigure 13c). After CS high is detect-
ed and the last data bit is transferred, the DAS is ready for a
new communication cycle to begin.
The timing diagrams in Figure 13 show the transfer of data
in packets of 8 bits (bytes). This represents the way the
serial ports of the 8051 family of microcontrollers produce
the serial clock and data. The DAS does not require a gap
between
the
first
and
second
bytes
of
the
data;
16 continuous clock cycles will transfer the data word. How-
ever, there should be a gap equal to 3 CLK (the DAS main
clock input, not the TXD clock) cycles between the end of
the command byte and the start of the data during a read
cycle. This is not concerned in most systems for two rea-
sons. First, the processor generally has some inherent gap
between byte transfers. Second, the TXD frequency is usu-
ally significantly slower than the CLK frequency. For exam-
ple, an 8051 processor with 12 MHz crystal generates a
TXD of 1 MHz. If the DAS is running with 6 MHz CLK, there
are 6 cycles of CLK within each cycle of TXD and the re-
quirement is satisfied even if TXD comes continuously after
command byte. The user should pay attention to this re-
quirement if running the TXD with a speed near or higher
than CLK.
TL/H/11879–40
(a) Write Cycle
Idle State of SCLK
e
1, Data Shifted at the Rising Edge of the SCLK
TL/H/11879–41
(b) Read Cycle
Idle State of SCLK
e
1, Data Shifted at the Rising Edge of the SCLK
FIGURE 13. Timing Diagrams for LM12434 and LM12
à
L
ó
438 8051 Serial Interface Mode
56
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LM12454 | General Purpose Controller Z84C15 |
| LM12454 | 12-Bit Sign Data Acquisition System with Self-Calibration |
| LM12454CIV | 12-Bit Sign Data Acquisition System with Self-Calibration |
| LM124AFK | CAP .0039UF 50V PPS FILM 1206 2% |
| LM324PT | OP-AMP|QUAD|BIPOLAR|TSSOP|14PIN|PLASTIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LM12438CIV | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Sign Data Acquisition System with Serial I/O and Self-Calibration |
| LM12438CIWM | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Sign Data Acquisition System with Serial I/O and Self-Calibration |
| LM12454 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:General Purpose Controller Z84C15 |
| LM12454_06 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:12-Bit + Sign Data Acquisition System with Self-Calibration |
| LM12454A WAF | 制造商:Texas Instruments 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。