參數(shù)資料
型號： LM9812CCV
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 模擬信號調(diào)理
英文描述： LM9812 30-Bit Color Linear CCD Sensor Processor
中文描述： SPECIALTY ANALOG CIRCUIT, PQCC52
封裝： PLASTIC, LCC-52
文件頁數(shù)： 5/37頁
文件大?。?/td> 479K
代理商： LM9812CCV
5
http://www.national.com
I
DI/O
Digital I/O Supply Current
Operating, V
DI/O
=5.0V
Standby, V
DI/O
= 5.0V
Operating, V
DI/O
=3.3V
Standby, V
DI/O
= 3.3V
12
5
2
0.3
30
20
10
3
mA (max)
mA (max)
mA (max)
mA (max)
AC Electrical Characteristics, MCLK Independent
The following specifications apply for AGND=DGND=DGND
I/O
=0V,
V
A
=
V
D
=
V
DI/O
=+5.0
V
DC
,
V
REF IN
= +2.0V
DC
, f
MCLK
=24MHz
,
t
MCLK
=1/f
MCLK
, t
r
=t
f
=5ns
, R
s
=25, C
L
(databus loading) = 50pF/pin.
Boldface limits apply for T
A
=T
J
=T
MIN
to T
MAX
; all other limits T
A
=T
J
=25°C. (Notes 7 & 8)
Symbol
Parameter
Conditions
Typical
(Note 9)
Limits
(Note 10)
Units
(Limits)
f
MCLK
Maximum MCLK Frequency
Minimum MCLK Frequency
24
4
MHz (min)
MHz (max)
MCLK Duty Cycle
40
60
% (min)
% (max)
t
SETUP (OUT)
Coefficient Data valid before latching
edge of OCLK or GCLK
GCLK and OCLK as
outputs
12
20
ns (min)
t
HOLD (OUT)
Coefficient Data held after latching
edge of OCLK or GCLK
GCLK and OCLK as
outputs
-10
0
ns (min)
t
SETUP (IN)
Coefficient Data Valid before latching
edge of OCLK or GCLK
GCLK and OCLK as
inputs
0
5
ns (min)
t
HOLD (IN)
Coefficient Data held after latching
edge of OCLK or GCLK
GCLK and OCLK as
inputs
0
5
ns (min)
t
GCLK-EOC
Rising edge of GLCK to falling edge
of EOC (GCLK as output)
2
ns
t
GCLK-OCLK
Rising edge of GLCK to falling edge
of OCLK (GCLK and OCLK as
outputs)
2 bus / 2 clock mode
1
ns
t
EOC-OCLK
Rising edge of EOC to rising edge of
OLCK (OCLK as output)
2 clock mode
1
ns
t
OCLK-GCLK
Rising edge of OLCK to falling edge
of GLCK (GCLK and OCLK as
outputs)
2 clock mode
3
ns
t
EOC-GCLK
Rising edge of EOC to falling edge of
GLCK (GCLK as output)
2 bus mode
2
ns
t
DACC
RD or RD_PIXEL low to D0-D9 data
valid
15
41
ns (max)
t
D1H, D0H
RD or RD_PIXEL high to D0-D9 data
tri-state
13
20
ns (max)
t
CS SETUP
CS setup of RD or WR
0
ns (min)
t
CS HOLD
CS hold after RD or WR
0
ns (min)
t
WR SETUP
D0-D9 data valid before rising edge
of WR (setup time)
5
ns (min)
DC and Logic Electrical Characteristics
(Continued)
The following specifications apply for AGND=DGND=DGND
I/O
=0V,
V
A
=
V
D
=
+5.0
V
, V
DI/O
=+5.0 or +3.3V
, V
REF IN
= +2.0V
DC
,
f
MCLK
=24MHz, R
s
=25
.
Boldface limits apply for T
A
=T
J
=T
MIN
to T
MAX
; all other limits T
A
=T
J
=25°C. (Notes 7 & 8)
Symbol
Parameter
Conditions
Typical
(Note 9)
Limits
(Note 10)
Units
(Limits)
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