參數(shù)資料
型號(hào)： LM9812CCV
廠(chǎng)商： NATIONAL SEMICONDUCTOR CORP
元件分類(lèi)： 模擬信號(hào)調(diào)理
英文描述： LM9812 30-Bit Color Linear CCD Sensor Processor
中文描述： SPECIALTY ANALOG CIRCUIT, PQCC52
封裝： PLASTIC, LCC-52
文件頁(yè)數(shù)： 7/37頁(yè)
文件大小： 479K
代理商： LM9812CCV
7
http://www.national.com
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional,
but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply
only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2:
All voltages are measured with respect to GND=AGND=DGND=DGND
I/O
=0V, unless otherwise specified.
Note 3:
When the input voltage (V
) at any pin exceeds the power supplies (V
<GND or V
>V
or V
), the current at that pin should be limited to 25mA. The 50mA max-
imum package input current rating limits the number of pins that can simultaneously safely exceed the power supplies with an input current of 25mA to two.
Note 4:
The maximum power dissipation must be derated at elevated temperatures and is dictated by T
max,
Θ
and the ambient temperature, T
. The maximum allow-
able power dissipation at any temperature is P
D
= (T
J
max - T
A
) /
Θ
JA
. T
J
max = 150°C for this device. The typical thermal resistance (
Θ
JA
) of this part when board mounted
is 52°C/W for the V52A PLCC package
.
Note 5:
Human body model, 100pF capacitor discharged through a 1.5k
resistor.
Note 6:
See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in any post 1986 National Semiconduc-
tor Linear Data Book for other methods of soldering surface mount devices.
Note 7:
A Zener diode clamps the OS analog inputs to AGND as shown below. This input protection, in combination with the external clamp capacitor and the output
impedance of the sensor, prevents damage to the LM9812 from transients during power-up.
Note 8:
To guarantee accuracy, it is required that V
A
and V
D
be connected together to the same power supply with separate bypass capacitors at each supply pin.
Note 9:
Typicals are at T
J
=T
A
=25°C, f
MCLK
= 24MHz, and represent most likely parametric norm.
Note 10:
Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 11:
Integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that best fits the actual transfer function of the ADC.
Note 12:
V
REF
is defined as the CCD OS voltage for the reference period following the reset feedthrough pulse. V
WHITE
is defined as the peak CCD pixel output voltage for
a white (full scale) image with respect to the reference level, V
.
V
is defined as the peak positive deviation above V
of the reset feedthrough pulse. The maximum
correctable range of pixel-to-pixel V
WHITE
variation is defined as the maximum variation in V
WHITE
(due to PRNU, light source intensity variation, optics, etc.) that the
t
EOC LOW
EOC low time
2*t
MCLK
ns
t
EOC HIGH
EOC high time
2*t
MCLK
ns
t
DATA VALID
D0-D9 data valid from falling
(Data
Read Phase = 0°)
or rising
(Data Read
Phase = 180°)
edge of EOC
4*t
MCLK
-20ns
ns (min)
t
OCLK-EOC 1
(OCLK IN)
OCLK rising edge to EOC falling edge
(Gain Coefficient Write Phase = 0°),
OCLK falling edge to EOC falling edge
(Gain Coefficient Write Phase = 180°)
1 bus mode w/ext OCLK
t
MCLK
+ 40ns
4*t
MCLK
ns (min)
ns (max)
t
OCLK-EOC 2
(OCLK IN)
OCLK rising edge to EOC rising edge
(Gain Coefficient Write Phase = 0°),
OCLK falling edge to EOC rising edge
(Gain Coefficient Write Phase = 180°)
2 bus mode w/ext OCLK
40ns
3*t
MCLK
ns (min)
ns (max)
t
GCLK-EOC
(GCLK IN)
GCLK rising edge to EOC falling edge
(Gain Coefficient Write Phase = 0°),
GCLK falling edge to EOC falling edge
(Gain Coefficient Write Phase = 180°)
w/ext GCLK
40ns
3*t
MCLK
ns (min)
ns (max)
AC Electrical Characteristics, MCLK Dependent
(Continued)
The following specifications apply for AGND=DGND=DGND
I/O
=0V,
V
A
=
V
D
=
V
DI/O
=+5.0
V
,
V
REF IN
= +2.0V
, f
=24MHz
,
t
=1/f
, t
r
=t
f
=5ns
, R
=25
, C
L
(databus loading) = 50pF/pin. Refer to Table 2: Configuration Register Parameters for limits
labeled C.R.
Boldface limits apply for T
A
=T
J
=T
MIN
to T
MAX
; all other limits T
A
=T
J
=25°C. (Notes 7 & 8)
Symbol
Parameter
Conditions
Typical
(Note 9)
Limits
(Note 10)
Units
(Limits)
To Internal
OS Input
AGND
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