5
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AC Electrical Characteristics
The following specifications apply for AGND=DGND=0V, V
A
=+5.0V
DC
,
V
D
=+3.0 or +5.0V
DC
, f
MCLK
=12MHz, except where noted
otherwise.
Boldface limits apply for
A
=T
J
=T
MIN
to T
MAX
; all other limits T
A
=T
J
=25°C.
(Notes 7& 8)
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional,
but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characte ristics. The guaranteed specifications apply
only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the list ed test conditions.
Note 2:
All voltages are measured with respect to GND=AGND=DGND=0V, unless otherwise specified.
Note 3:
When the input voltage (V
) at any pin exceeds the power supplies (V
<GND or V
>V
or
V
), the current at that pin should be limited to 25mA. The 50m
maximum package input current rating limits the number of pins that can simultaneously safely exceed the power supplies with an input current of 25mA to two.
Note 4:
The maximum power dissipation must be derated at elevated temperatures and is dictated by T
max,
Θ
and the ambient temperature, T
. The maximum allow-
able power dissipation at any temperature is P
D
= (T
J
max - T
A
) /
Θ
JA
. T
J
max = 150°C for this device. The typical thermal resistance (
Θ
JA
) of this part when board mounted
is 69°C/W for the M28B SOIC package
Note 5:
Human body model, 100pF capacitor discharged through a 1.5k
resistor. Machine model, 200 pF capacitor discharged through a 0
resistor.
Note 6:
See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in any National Semiconductor Linear
Data Book for other methods of soldering surface mount devices.
Note 7:
Two diodes clamp the OS analog inputs to
AGND
and
V
as shown below. This input protection, in combination with the external clamp capacitor and the output
impedance of the sensor, prevents damage to the LM9822 from transients during power-up.
Note 8:
To guarantee accuracy, it is required that V
and V
be connected to clean, low noise power supplies, with separate bypass capacitors at each supply pin. When
both V
A
and V
D
are operated at 5.0V, they must be powered by the same regulator, with separate power planes or traces and separate bypass capacitors at each supply pin.
Symbol
Parameter
Conditions
Typical
(Note 9)
Limits
(Note 10)
Units
(Limits)
f
MCLK
Maximum MCLK frequency
12
MHz (min)
t
MCLK
MCLK period
83
ns (min)
MCLK duty cycle
40
60
%(min)
%(max)
t
SCLK
Serial Clock Period
1
t
MCLK
(min)
t
SEN
Serial Enable high time
3
t
MCLK
(min)
t
SSU
SDI setup time
1
ns (min)
t
SH
SDI hold time
3
ns (min)
t
SDDO
SCLK
edge to new valid data
V
D
= 5.0V
V
D
= 3.3V
8.5
19
20
ns (max)
t
VSU
VSMP setup time
1
ns (min)
t
VH
VSMP hold time
3
ns (min)
t
CSU
CLMP setup time
1
ns (min)
t
CH
CLMP hold time
3
ns (min)
t
DDO
MCLK
edge to new valid data
V
D
= 5.0V
V
D
= 3.3V
16
25
25
ns (max)
ns (max)
OS Input
AGND
V
A
TO INTERNAL
CIRCUITRY