參數(shù)資料
型號: LM9833CCVJD
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 消費(fèi)家電
英文描述: LM9833 48-Bit Color, 1200dpi USB Image Scanner
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝: PLASTIC, TQFP-100
文件頁數(shù): 3/42頁
文件大小: 547K
代理商: LM9833CCVJD
3
www.national.com
Pin Descriptions
USB Interface
D+, D-
Digital I/O. USB Interface signals
BUS POWER
Digital Input. Tie low for bus powered sys-
tems, tie high for external power.
ACTIVE/
SUSPENDED
Digital Output. Low in Suspend mode. High in
operational mode. Used to control external
regulators, other components.
SDA
Digital I/O. Serial Data to/from external
EEPROM.
SCL
Digital Output. Serial Clock Output to external
EEPROM.
Analog
OS
R
,
OS
G
,
OS
B
Analog Inputs. These inputs (for Red, Green,
and Blue) should be tied to the sensor’s out-
put signal through DC blocking capacitors. If
unused, tie to ground through DC blocking
capacitors.
V
REF LO
Analog Output/Input. Bypass to AGND with a
0.047μF monolithic capacitor. Do not put a
DC load on this pin.
V
REF MID
Analog Output/Input. Bypass to AGND with a
0.047μF monolithic capacitor. Do not put a
DC load on this pin.
V
REF HI
Analog Output/Input. Bypass to AGND with a
0.047μF monolithic capacitor. Do not put a
DC load on this pin.
V
BANDGAP
Analog Output. Bypass to AGND with a
0.047μF monolithic capacitor. Do not put a
DC load on this pin.
DRAM
D0 (LSB) -D15
(MSB)
Digital Inputs/Outputs. This is the 16 bit data
path between the external DRAM and the
LM9833.
RD
Digital Output. Read signal to external DRAM.
WR
Digital Output. Write signal to external DRAM.
A0-A9
Digital Outputs. Address pins for up to 1M x
16 external DRAM.
RAS
Digital Output. Row Address Strobe signal.
CAS
Digital Output. Column Address Strobe sig-
nal.
Scanner Support I/O
PAPER
SENSE 1-2
Digital Inputs. Programmable, used for sens-
ing home position, paper, front panel
switches, etc.
MISC I/O 1-6
Digital Inputs/Outputs. Programmable, used
for front panel switches, status LEDs, etc. At
power-on and in Suspend Mode, MISC I/Os
1-3 are inputs and MISC I/Os 4-6 are outputs.
Stepper Motor
A, B, A, B
Digital Outputs. Pulses to stepper motor drive
circuitry.
SENSE
A
,
SENSE
B
SENSE
GND
Analog Inputs. Current sensing for stepper
motor’s PWM current control.
Analog Input. Ground sense input for stepper
motor’s PWM current control.
Sensor Control
1
Digital Output. CCD/CIS clock signal phase 1.
2
Digital Output. CCD/CIS clock signal phase 2.
RS
Digital Output. Reset pulse for the CCD/CIS.
CP1
Digital Output. Clamp pulse for the CCD/CIS.
CP2
Digital Output. Clamp pulse for the CCD/CIS.
TR1, TR2
Digital Outputs. Transfer pulses for the
CCD/CIS.
LAMP
R
,
LAMP
G
,
LAMP
B
Digital Outputs. Used to control R, G, and B
LEDs of single output CIS, as well as bright-
ness of CCFL. The CDS signal can be seen
on LAMP
B
in a test mode (see register 5E, bit
7).
Master Clock Generation
CRYSTAL IN
Digital Input. Used with CRYSTAL OUT and
an external 48MHz crystal to form a crystal
oscillator.
CRYSTAL
OUT
Digital Output. Used with CRYSTAL IN and an
external 48MHz crystal to form a crystal oscil-
lator.
CRYSTAL/
EXT CLOCK
Digital Input. Tie to DGND for operation with
an external crystal. Pull up to V
to drive
CRYSTAL OUT with an external TTL or
CMOS clock source.
24/48
Digital Input. Tie to DGND for operation with a
48MHz crystal or external clock. Pull up to V
D
for operation with a 24MHz crystal or external
clock. NOTE: Operation at 24MHz is not guar-
anteed - always use a 48MHz crystal.
Miscellaneous
V
REGULATOR
Digital Output. This is the regulated 3.3V sup-
ply (generated from V
D
) that powers the USB
transceiver. It should be used as the terminal
voltage for the 1.5k D+ pullup resistor, and
bypassed to DGND with a 0.047μF monolithic
capacitor.
RESET
Digital input. Take high to force device into
Power On Reset state, low to exit reset state.
TEST
Analog Output.
CMODE
Digital Input. Test mode, always tie high.
L
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