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參數(shù)資料
| 型號： | LM98503CCVV |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 10-Bit, 18 MSPS Camera Signal Processor |
| 中文描述： | 10位，18 MSPS的攝像機(jī)信號處理器 |
| 文件頁數(shù)： | 15/25頁 |
| 文件大?。?/td> | 203K |
| 代理商： | LM98503CCVV |
www.national.com
15
System Overview
(continued)
referred to as CLAMP and SAMPLE.These signals provide the
rising edge reference for the sampling of the CCD input signal.
The timing of CLAMP and SAMPLE is derived from the clock;
therefore, shifting the clock phasing with respect to the CCD
input signal would also shift the rising (and falling) edges of
CLAMP and SAMPLE. The actual sampling of the CCD’s reset
voltage and video signal is performed on the falling edges of the
CLAMP and SAMPLE signals respectively. The user may modify
the position of the falling edges where the sampling of the CCD
input occurs by driving the SHP and SHD inputs of the
LM98503. The falling edges of SHP and SHD will supersede the
falling edges of CLAMP and SAMPLE respectively and cause
the duration of the sample pulse to shorten accordingly. As
evidenced in Figure 4 and Figure 5, the falling edges of SHP
and SHD should not occur earlier than t
SHP
or t
SHD
after the
respective falling [SHP] (or rising [SHD]) edge of CLK.
1.6 Serial Interface and Configuration Registers
There are many options available to the user that may be
programmed via the LM98503’s serial interface. Configuration
values are stored in registers for use by several functions such
as programmable gain, offset, black level, and color filter array.
The LM98503’s serial interface is used to store values into 16 8-
bit configuration registers. Upon power-up or external reset, the
configuration registers will contain their respective default
values. Default values place the LM98503 in ‘single channel’
mode, where only one PGA gain and offset are applied to the
input signal.
The master CLK input is required to be running during serial
interface commands. Each command issued through the serial
interface must have a minimum of 13 data bits (see Figure 12
and Figure 13).
1.7 PGA Gain Registers
Four PGA gain registers store four possible gain values for the
programmable gain amplifier (PGA). For example, these four
gain values may correspond to four possible colors in a color
filter array.
1.8 Analog Offset
Four analog offset registers store four possible offset values that
correspond to the four PGA gain values. For example, the value
stored in the PGA gain register 0 (address 0h) is used in
conjunction with the offset value stored in the analog offset
register 0 (address 4h). This allows for four possible
combinations of PGA gain and analog offset, one for each color
filter. These registers are read-only when offset auto-calibration
is enabled in the software control register 0. It should be noted
that each offset DAC step (1 LSB) corresponds to a 0.4 LSB
step at the ADC output. Therefore, if an offset of 20 digital codes
is desired at the ADC output, a digital code value of 50 should
be stored in the analog offset register(s). As a result, the
maximum offset seen at the ADC output as a result of digital
code values stored in the analog offset register(s) is
±
54 codes.
It is possible to increase the digital output range of the analog
offset DAC, resulting in an increased maximum ADC output
code corresponding to a given DAC input, but at the expense of
DAC step resolution. For more information on increasing the
DAC range, please see “Analog Offset DAC Range Adjustment”
on page 23.
1.9 Output Black Level
The output black level register is occupied by an 8-bit word
stored by the user that specifies the output level corresponding
to optical black. For example, a user that wants an output level
of 16 for black pixels must write this value into the register
during the horizontal interval. Note that it is not recommended
that a value of 0 be stored as the output black level. Once this
has been accomplished, driving the BLKCLP high for 20 cycles
of CLK activates the digital black clamp loop and the black level
is forced to the value stored in the output black level register, in
the example case the code value of 16. As a result of the
relationship between the DAC input and the ADC output, under
default conditions the largest black level code the LM98503 is
capable of clamping to is 36 codes. As a result, the offset DAC
may be ‘pinned’ at full range when the default setting of 32 is
used. When this occurs, the result may be that the DAC is
unable to correct line to line variations in the black level.
consequently, horizontal lines or ‘banding’ may be observed.
See Analog Offset DAC Range Adjustment, Section 3.0 of the
applications information for instructions on how to increase this
range
.
Figure 11: ADC Output vs. Black Level Register Value
1.10 Color Filter Array (CFA) Configuration
In order to utilize the LM98503’s programmable pixel-rate gain,
a color filter array (CFA) pattern must be defined. Some
commonly used CFA patterns are as follows:
Therefore, two 8-bit words must be written to the CFA line
registers to specify the CFA pattern being used. Also, two 2-bit
numbers must be written to the CFA definition register indicating
the number of pixels per pattern in each line of the defined CFA
pattern. The information contained in the CFA line registers
indicates the registers where the respective PGA gain and offset
values are stored. For example, a system using the Bayer
pattern defined above would first write four PGA gains and their
respective offsets into the four PGA gain and four analog offset
registers. Next, two 8-bit words (one word/CFA line) would be
written to the CFA configuration registers. The 8-bit CFA
configuration words each consist of four 2-bit numbers, each of
which is the address for the gain and offset values of the of the
color that appears in that location in the CFA line. Finally, two 2-
bit numbers specifying the number of elements in each CFA line
must be written into the CFA definition register. A CFA
configuration will then contain four 2-bit numbers indicating the
registers where the gain and offset values are located for a
Bayer Pattern
Line 0
Line 1
Green
Blue
Red
Green
Green
Blue
Red
Green
CMYG Pattern
Line 0
Line 1
Cyan
Cyan
Magenta
Green
Yellow
Yellow
Green
Magenta
0
10
20
30
40
50
60
0
15
30
45
60
75
Output Black Level Register Value
90
105
120
135
150
165
180
195
210
225
240
255
A
Default Black Level
LM98501, LM98502
LM98503
L
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