參數(shù)資料
型號(hào)： LM98503CCVV
廠商： National Semiconductor Corporation
英文描述： 10-Bit, 18 MSPS Camera Signal Processor
中文描述： 10位，18 MSPS的攝像機(jī)信號(hào)處理器
文件頁(yè)數(shù)： 8/25頁(yè)
文件大?。?/td> 203K
代理商： LM98503CCVV
www.national.com
8
Analog to Digital Converter Specifications
The following specifications apply for DV+ = AV+ = DV+ I/O = +3.0V, C
L
= 10pF, and f
CLK
= 18 MHz unless otherwise noted.
Boldface
limits apply for TA = T
MIN
to T
MAX
:
all other limits T
A
= 25
o
C (Note 7)
AC Electrical Characteristics
The following specifications apply for DV+ = AV+ = DV+ I/O = +3.0V, C
L
= 10pF, and f
CLK
= 18 MHz unless otherwise noted.
Boldface
limits apply for TA = T
MIN
to T
MAX
:
all other limits T
A
= 25
o
C (Note 7)
Full Channel Performance Specifications
The following specifications apply for AV+ = DV+ = DV+ I/O = 3.0V, C
L
= 10pF, and f
CLK
= 18MHz unless otherwise noted.
Boldface
limits apply for TA = T
MIN
to T
MAX
:
all other limits T
A
= 25
o
C (Note 7)
* Note:
Note 1:
20 log
10
(V
IN
/ RMS Output Noise)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate con-
ditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications
and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions
listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.
When the voltage at any pin exceeds the power supplies (VIN < GND or VIN > AV+ or DV+), the current at that pin should
be limited to 35mA. The 50mA maximum package input current rating limits the number of pins that can safely exceed the
power supplies with an input current of 25mA to two.
Note 2:
Note 3:
Symbol
Parameter
Conditions
Min
(note 9)
Typical
(note 8)
Max
(note 9)
Units
R
REF
Reference Ladder Resistance
1000
k
V
REFT
Top of Reference Ladder
V
REFT
not driven
externally.
2.25
V
V
REFB
Bottom of Reference Ladder
V
REFB
not driven
externally.
0.75
V
V
REFT
-
V
REFB
Differential Reference Voltage
V
REFT
and V
REFB
not
driven externally.
1.5
V
Overrange Output Code
V
IN
> V
REFT
1023
Underrange Output Code
V
IN
< V
REFB
0
Symbol
Parameter
Conditions
Min
(note 9)
Typical
(note 8)
Max
(note 9)
Units
Symbol
Parameter
Conditions
Min
(note 9)
Typical
(note 8)
Max
(note 9)
Units
f
CLK
Input Clock Frequency
1
18
20
MHz
T
CLK
Input Clock Period
50
55
1000
ns
t
ch
Clock High Time
@ CLK
max
27.5
ns
t
cl
Clock Low Time
@ CLK
max
22.5
ns
Clock Duty Cycle
@ CLK
max
45/55
min/max
t
rc
, t
fc
Clock Input Rise and Fall Time
5
ns
Pipeline Delay (Latency)
7
T
CLK
t
VALID
Data valid time
40
ns
t
OH
Output Data Hold Time
27
33
ns
t
OD
Output Delay Time
20
ns
Symbol
Parameter
Conditions
Min
(note 9)
Typical
(note 8)
Max
(note 9)
Units
DNL
Differential Non-Linearity
±
0.5
LSB
INL
Integral Non-Linearity
+3.0/-1.5
LSB
L
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