參數(shù)資料
型號(hào)： LM98503CCVV
廠商： National Semiconductor Corporation
英文描述： 10-Bit, 18 MSPS Camera Signal Processor
中文描述： 10位，18 MSPS的攝像機(jī)信號(hào)處理器
文件頁(yè)數(shù)： 18/25頁(yè)
文件大?。?/td> 203K
代理商： LM98503CCVV
www.national.com
18
Register Data
(continued)
Register Name Analog Offset 1
Address
5 Hex
Type
Read/Write
Reset Value
0000 0000 Binary
Register Name Analog Offset 2
Address
Type
Reset Value
6 Hex
Read/Write
0000 0000 Binary
Register Name Analog Offset 3
Address
Type
Reset Value
7 Hex
Read/Write
0000 0000 Binary
4.0 Color Filter Array Registers
Register Name Color Filter Array Configuration 0
Address
8 Hex
Type
Read/Write
Reset Value
0000 0000 Binary
Register Name Color Filter Array Configuration 1
Address
9 Hex
Type
Read/Write
Reset Value
0000 0000 Binary)
Register Name Color Filter Array Definition
Address
A Hex
Type
Read/Write
Reset Value
XXXX 0000 Binary
5.0 Output Black Level Register
Register Name Output Black Level
Address
B Hex
Type
Read/Write
Reset Value
0001 0000 Binary
6.0 Software Control Registers
Register Name Software Control 0 (Customer)
Address
C Hex
Type
Read/Write
Reset Value
0100 1110 Binary
Bit
Bit Symbol
Description
[7:0]
Signed Analog
Offset
Digital representation of the
analog offset to be applied to
the input of the PGA. See
“Analog Offset” on page 15.
Bit
Bit Symbol
Description
[7:0]
Signed Analog
Offset
Digital representation of the
analog offset to be applied to
the input of the PGA. See
“Analog Offset” on page 15.
Bit
Bit Symbol
Description
[7:0]
Signed Analog
Offset
Digital representation of the
analog offset to be applied to
the input of the PGA. See
“Analog Offset” on page 15.
Bit
Bit Symbol
Description
[7:6]
Line0:Pixel3
Gain/Offset
2 LSB’s of register addresses
where the gain and offset for pixel
3 of the CFA pattern are stored.
[5:4]
Line0:Pixel2
Gain/Offset
2 LSB’s of register addresses
where the gain and offset for pixel
2 of the CFA pattern are stored.
[3:2]
Line0:Pixel 1
Gain/Offset
2 LSB’s of register addresses
where the gain and offset for pixel
1 of the CFA pattern are stored.
[1:0]
Line0:Pixel0
Gain/Offset
2 LSB’s of register addresses
where the gain and offset for pixel
0 of the CFA pattern are stored.
Bit
Bit Symbol
Description
[7:6]
Line1:Pixel3
Gain/Offset
2 LSB’s of register addresses
where the gain and offset for pixel
3 of the CFA pattern are stored.
[5:4]
Line1:Pixel2
Gain/Offset
2 LSB’s of register addresses
where the gain and offset for pixel
2 of the CFA pattern are stored.
[3:2]
Line1:Pixel 1
Gain/Offset
2 LSB’s of register addresses
where the gain and offset for pixel
1 of the CFA pattern are stored.
[1:0]
Line1:Pixel0
Gain/Offset
2 LSB’s of register addresses
where the gain and offset for pixel
0 of the CFA pattern are stored.
Bit
Bit Symbol
Description
[3:2]
Line 1 Pixels
Number of pixels in CFA pattern
defined in CFA line 1.
[2:1]
Line 0 Pixels
Number of pixels in CFA pattern
defined in CFA line 0.
Bit
Bit Symbol
Description
[7:0]
Black Level
0 - 256 output black level digital
code value. (see “Output Black
Level” on page 15)
Bit
Bit Symbol
Description
[7]
Offset
Output
Enable
Directs the offset error calculated
by the digital black level correction
loop to the 10 digital output data
pins.
[6]
Serial
Output
Enable
Enables the serial interface output
for reading register values.
L
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