參數(shù)資料
型號(hào)： LMX2306
廠商： National Semiconductor Corporation
英文描述： PLLatinum Low Power Frequency Synthesizer for RF Personal Communications(PLLatinum技術(shù)用于射頻個(gè)人通訊的低耗頻率合成器)
中文描述： PLLatinum頻率合成器的低功耗射頻個(gè)人通信（PLLatinum技術(shù)用于射頻個(gè)人通訊的低耗頻率合成器）
文件頁(yè)數(shù)： 10/19頁(yè)
文件大小： 300K
代理商： LMX2306
1.0 Functional Description
(Continued)
1.3.1 POWERDOWN OPERATION
Bits F[2] and F[18] provide programmable powerdown modes when the CE pin is HIGH. When CE is LOW, the part is always im-
mediately disabled regardless of powerdown bit status. Refer to Table 3
Synchronous and asynchronous powerdown modes are both available by MICROWIRE selection. Synchronous powerdown oc-
curs if the F[18] bit (Powerdown Mode) is HIGH when F[2] bit (Powerdown) becomes HIGH. Asynchronous powerdown occurs
if the F[18] bit is LOW when its F[2] bit becomes HIGH.
In the synchronous powerdown mode (F[18] = HIGH), the powerdown function is gated by the charge pump to prevent unwanted
frequency jumps. Once the powerdown program bit F[2] is loaded, the part will go into powerdown mode after the first successive
charge pump event.
In the asynchronous powerdown mode (F[18] = LOW), the device powers down immediately after latching LOW data into bit F[2].
The device returns to an actively powered up condition in either synchronous or asynchronous mode immediately upon LE latch-
ing LOW data into bit F[2].
Activation of a powerdown condition in either synchronous or asynchronous mode including CE pin activated powerdown has the
following effects:
Removes all active DC current paths.
Forces the R, N, and timeout counters to their load state
conditions.
Will TRI-STATE the charge pump.
Resets the digital lock detect circuitry.
Debiases the f
IN
input to a high impedance state.
Disables the oscillator input buffer circuitry.
The MICROWIRE control register remains active and ca-
pable of loading the data.
TABLE 3. Power Down Truth Table
CE(Pin 10)
F[2]
X
0
1
1
F[18]
X
X
0
1
Mode
LOW
HIGH
HIGH
HIGH
Asynchronous Power Down
Normal Operation
Asynchronous Power Down
Synchronous Power Down
TABLE 4. The Fo/LD (pin 14) Output Truth Table
F[3]
0
0
0
0
1
1
F[4]
0
0
1
1
0
0
F[5]
0
1
0
1
0
1
Fo/LD Output State
TRI-STATE
R Divider Output (fr)
N Divider Output (fp)
Serial Data Output
Digital Lock Detect (See 1.3.2 LOCK DETECT OUTPUT Section)
n Channel Open Drain Lock Detect (See 1.3.2 LOCK DETECT OUTPUT
Section)
Active HIGH
Active LOW
1
1
1
1
0
1
L
www.national.com
10
相關(guān)PDF資料
PDF描述
LMX2322 PLLatinumTM 2.0 GHz Frequency Synthesizer for RF Personal Communications
LMX2332LSLDX PLLatinumTM Low Power Dual Frequency Synthesizer for RF Personal Communications
LMX2330LSBX PLLatinumTM Low Power Dual Frequency Synthesizer for RF Personal Communications
LMX2330LSLDX PLLatinumTM Low Power Dual Frequency Synthesizer for RF Personal Communications
LMX2331LSLDX PLLatinumTM Low Power Dual Frequency Synthesizer for RF Personal Communications
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LMX2306_04 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinum⑩ Low Power Frequency Synthesizer for RF Personal Communications
LMX2306LBX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FREQUENCY SYNTHESIZER|BICMOS|LLCC|16PIN|PLASTIC
LMX2306SLBX 制造商:Texas Instruments 功能描述:PLL Frequency Synthesizer Single 25MHz to 550MHz 16-Pin LAM CSP T/R
LMX2306SLBX/NOPB 功能描述:IC FREQ SYNTH 16LAMINATE CSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:*
LMX2306TM 制造商:Texas Instruments 功能描述:PLL Frequency Synthesizer Single 25MHz to 550MHz 16-Pin TSSOP Rail 制造商:Texas Instruments 功能描述:550MHZ SINGLE PLL 2306 TSSOP16
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*