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參數(shù)資料
| 型號(hào)： | LMX2322 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | PLLatinumTM 2.0 GHz Frequency Synthesizer for RF Personal Communications |
| 中文描述： | PLLatinumTM 2.0千兆赫頻率合成射頻個(gè)人通信 |
| 文件頁(yè)數(shù)： | 6/14頁(yè) |
| 文件大?。?/td> | 227K |
| 代理商： | LMX2322 |
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LMX2322
1.0 Functional Description
Advance Information
Rev 1.6
9/24/1998
6
The basic phase-lock-loop (PLL) configuration consists of a high-stability crystal reference oscillator, a
frequency synthesizer such as the National Semiconductor LMX2322, a voltage controlled oscillator (VCO), and
a passive loop filter. The frequency synthesizer includes a phase detector, current mode charge pump, as well
as programmable reference [R] and feedback [N] frequency dividers. The VCO frequency is established by
dividing the crystal reference signal down via the R counter to obtain a frequency that sets the comparison
frequency. This reference signal, fr, is then presented to the input of a phase/frequency detector and compared
with another signal, fp, the feedback signal, which was obtained by dividing the VCO frequency down by way of
the N counter. The phase/frequency detector's current source outputs pump charge into the loop filter, which
then converts the charge into the VCO's control voltage. The phase/frequency comparator’s function is to
adjust the voltage presented to the VCO until the feedback signal’s frequency (and phase) match that of the
reference signal. When this ‘phase-locked’ condition exists, the RF VCO’s frequency will be N times that of the
comparison frequency, where N is the divider ratio.
Oscillator
1.1
The reference oscillator frequency for the PLL is provided by an external reference TCXO through the OSCin
pin. OSCin block can operate to 40MHz with a minimum input sensitivity of 0.4Vpp. The inputs have a Vcc/2
input threshold and can be driven from an external CMOS or TTL logic gate.
Reference Divider (R Counter)
1.2
The R Counter is clocked through the oscillator block. The maximum input frequency is 40MHz and the
maximum output frequency is 10MHz. The R Counters is a 10 bit CMOS binary counters with a divide range
from 2 to 1,023. See programming description 2.2.1.
Programmable Divider (N Counter)
1.3
The N counter is clocked by the small signal fin input. The LMX2322 RF N counter is a 15 bit integer divider.
The N counter is configured as a 5 bit A Counter and a 10 bit B Counter, offering a continuous integer divide
range from 992 to 32,767. The LMX2322 is capable of operating from 700MHz to 2.0GHz with a 32/33 precaler.
1.3.1 Prescaler
The RF inputs to the prescaler consist of the fin and fin pins which are the complimentary inputs of a differential
pair amplifier. The differential fin configuration can operate to 2GHz with a minimum input sensitivity of
45mVrms. The input buffer drives A counter’s ECL D-type flip-flops in a dual modulus configuration. The
LMX2322 has a 32/33 prescaler ratio. The prescaler clocks the subsequent CMOS flip-flop chain comprising
the fully programmable A and B counters
.
1.4 Phase/Frequency Detector
The phase/frequency detector is driven from the N and R counter outputs. The maximum frequency at the
phase detector inputs is 10 MHz. The phase detector outputs control the charge pumps. The polarity of the
pump-up or pump-down control is programmed using PD_POL, depending on whether RF VCO characteristics
are positive or negative (see programming description 2.2.2). The phase detector also receives a feedback
signal from the charge pump, in order to eliminate dead zone.
Charge Pump
1.5
The phase detector's current source output pumps charge into an external loop filter, which then converts the
charge into the VCO's control voltage. The charge pumps steer the charge pump output, Cpo, to Vcc (pump-up)
or Ground (pump-down). When locked, Cpo is primarily in a Tri-state mode with small corrections. The RF
charge pump output current magnitude is set to 4.0mA. The charge pump output can also be used to output
divider signals as detailed in section 2.2.3.
Microwire Serial Interface
1.6
The programmable functions are accessed through the Microwire serial interface. The interface is made of three
functions: clock, data and latch enable (LE). Serial data for the various counters is clocked in from data on the
rising edge of clock, into the 18- bit shift register. Data is entered MSB first. The last bit decodes the internal
register address. On the rising edge of LE, data stored in the shift register is loaded into one of the two
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