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參數(shù)資料
| 型號： | LMX2322 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | PLLatinumTM 2.0 GHz Frequency Synthesizer for RF Personal Communications |
| 中文描述： | PLLatinumTM 2.0千兆赫頻率合成射頻個(gè)人通信 |
| 文件頁數(shù)： | 8/14頁 |
| 文件大?。?/td> | 227K |
| 代理商： | LMX2322 |
LMX2322
2.0 Programming Description
Advance Information
Rev 1.6
9/24/1998
8
2.1
MICROWIRE
TM
Interface
The MICROWIRE
TM
interface is comprised of an 18 bit shift register, a R register and a N register. The shift
register consists of a 17 bit DATA field and a 1 bit address (ADDR) field as shown below. When Latch Enable
transitions HIGH, data stored in the shift register is loaded into either the R or N register depending on the ADDR
bit as described in Table 2.1.1. The data is loaded MSB first. The DATA field assignment for the R and N
registers are shown in Table 2.1.2 below.
MSB LSB
DATA [16:0]
17 1 0
ADDR
2.1.1
Address bit Truth Table
When LE is transitioned high, data is transferred from the 18-bit shift register into either the 14-bit R register, or
the 17 bit N register depending upon the state of the ADDR bit.
ADDR
DATA Location
0
N register
1
R register
2.1.2
Register Content Truth Table
First Bit SHIFT REGISTER BIT LOCATION Last Bit
17 16 15
14
13
12
11
10 9 8 7 6 5 4 3
2
1
0
N register
NB_CNTR
NA_CNTR
CTL_WORD
0
R register
X X X TEST RS PD_POL CP_TRI
R_CNTR
1
2.2 R REGISTER
If the Address Bit (ADDR) is 1, when LE is transitioned high data is transferred from the 18-bit shift register into
the 14-bit R register. The R register contains a latch which sets the PLL 10-bit R counter divide ratio. The divide
ratio is programmed using the bits R_CNTR as shown in Table 2.2.1. The ratio must be
≥
2. The PD_POL,
CP_TRI and TEST bits control the phase detector polarity, charge pump tri-state, and test mode respectively, as
shown in Table 2.2.2 . The RS bit is reserved and should always be set to zero. X denotes a don’t care condition.
First Bit SHIFT REGISTER BIT LOCATION Last Bit
17 16 15
14
13
12
11
10 9 8 7 6 5 4 3
2
1
0
X X X TEST RS PD_POL CP_TRI
R_CNTR[9:0]
1
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