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參數(shù)資料
| 型號： | LMX2470SLEX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | 2.6 GHz Delta-Sigma Fractional-N PLL with 800 MHz Integer-N PLL |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 2600 MHz, PQCC24 |
| 封裝： | CSP-24 |
| 文件頁數(shù)： | 20/36頁 |
| 文件大?。?/td> | 453K |
| 代理商： | LMX2470SLEX |
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Functional Description
(Continued)
1.5 PCB LAYOUT CONSIDERATIONS
Power Supply Pins
For these pins, it is recommended that
these be filtered by taking a series 18 ohm resistor and then
placing two capacitors shunt to ground, thus creating a low
pass filter. Although it makes sense to use large capacitor
values in theory, the ESR ( Equivalent Series Resistance ) is
greater for larger capacitors. For optimal filtering minimize
the sum of the ESR and theoretical impedance of the ca-
pacitor. It is therefore recommended to provide two capaci-
tors of very different sizes for the best filtering. 0.1 μF and
100 pF are typical values. The charge pump supply pins in
particular are vuvulnerablenerable to power supply noise.
High Frequency Input Pins, FinRF and FinIF
The signal
path from the VCO to the PLL is the most sensitive and
challenging for board layout. It is generally recommended
that the VCO output go through a resistive pad and then
through a DC blocking capacitor before it gets to these high
frequency input pins. If the trace length is sufficiently short (
<
1/10th of a wavelength ), then the pad may not be neces-
sary, but a series resistor of about 39 ohms is still recom-
mended to isolate the PLL from the VCO. The DC blocking
capacitor should be chosen at least to be 100 pF. It may turn
out that the frequency in this trace is above the self-resonant
frequency of the capacitor, but since the input impedance of
the PLL tends to be capacitive, it actually be a benefit to
exceed the self-resonant frequency. The pad and the DC
blocking capacitor should be placed as close to the PLL as
possible
Complimentary High Frequency Pin, FinRF*
These inputs
may be used to drive the PLL differentially, but it is very
common to drive the PLL in a single ended fashion. A shunt
capacitor should be placed at the FinRF* pin. The value of
this capacitor should be chosen such that the impedance,
including the ESR of the capacitor, is as close to an AC short
as possible at the operating frequency of the PLL. 100 pF is
a typical value.
1.6 FASTLOCK AND CYCLE SLIP REDUCTION
The LMX2470 has enhanced features for Fastlock and cycle
slip operation. The next several sections discuss the the
benefits of using both of these features. There are four
possible combinations that are possible, and these are
shown in the table below:
Charge Pump Current
Keep Comparison
Frequency the Same
Decrease Comparison
Frequency (CSR)
(RF Side Only)
CSR/Fastlock Combination
Engaging the CSR does decrease the
loop bandwidth during frequency
acquisition, but may be necessary to
reduce cycle slipping. By also
increasing the charge pump current, this
can compensate for the reduce loop
bandwidth due to the CSR
CSR Only
This mode is not generally
recommended, but may reduce cycle
slipping in some applications. Although
the theoretical lock time is decreased,
due to the decreased loop bandwidth
during Fastlock, cycle slips can be
reduced or eliminated.
Increase Charge Pump Current
Classical Fastlock
Allows the loop bandwidth to be
increased. This has a frequency glitch
caused by switching the charge pump
currents, but there is no frequency glitch
caused by switching from fractional to
integer mode
Keep Charge Pump Current the Same
Operation with No Fastlock
This mode represents using no Fastlock
Decrease Charge Pump Current
It never makes sense to use a lower
charge pump current during Fastlock
than in the steady state.
Note
that if the charge pump current and cycle slip reduction circuitry are engaged in the same proportion, then it is not necessary
to switch in a Fastlock resistor and the loop filter will be optimized for both normal mode and Fastlock mode. For third and fourth
order filters which have problems with cycle slipping, this may prove to be the optimal choice of settings.
L
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相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LMX2485 | 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL |
| LMX2485E | 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL |
| LMX2485ESQ | 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL |
| LMX2485ESQX | 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL |
| LMX2485SQ | 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LMX2470SLEX/NOPB | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| LMX2471 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:3.6 GHz Delta-Sigma Fractional-N PLL with 1.7 GHz Integer-N PLL |
| LMX2471 WAF | 制造商:Texas Instruments 功能描述: |
| LMX2471SLEX | 功能描述:IC PLL LP 3.6GHZ/1.7GHZ 24-CSP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| LMX2471SLEX/NOPB | 制造商:Texas Instruments 功能描述:PLL Dual 250MHz to 3600MHz 24-Pin LAM CSP T/R |
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