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參數(shù)資料
| 型號(hào)： | LMX2470SLEX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類(lèi)： | XO, clock |
| 英文描述： | 2.6 GHz Delta-Sigma Fractional-N PLL with 800 MHz Integer-N PLL |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 2600 MHz, PQCC24 |
| 封裝： | CSP-24 |
| 文件頁(yè)數(shù)： | 5/36頁(yè) |
| 文件大?。?/td> | 453K |
| 代理商： | LMX2470SLEX |
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Electrical Characteristics
(V
CC
= 2.5V; -40C
≤
T
A
≤
+85C unless otherwise specified) (Continued)
Symbol
Parameter
Conditions
Value
Typ
Units
Min
Max
DIGITAL INTERFACE (DATA, CLK, LE, EN, ENRF, Ftest/LD, FLoutRF, FLoutIF)
V
OL
Low-Level Output Voltage
MICROWIRE INTERFACE TIMING
T
CS
Data to Clock Set Up Time
T
CH
Data to Clock Hold Time
T
CWH
Clock Pulse Width High
T
CWL
Clock Pulse Width Low
T
ES
Clock to Load Enable Set
Up Time
T
EW
Load Enable Pulse Width
PHASE NOISE
L
F1Hz
RF
RF Synthesizer Normalized
Phase Noise Contribution
(Note 3)
I
OL
= 500 μA
0.4
V
See Microwire Input Timing
See Microwire Input Timing
See Microwire Input Timing
See Microwire Input Timing
See Microwire Input Timing
50
10
50
50
ns
ns
ns
ns
50
ns
See Microwire Input Timing
50
ns
RF_CPG = 0
RF_CPG = 3
RF_CPG = 7
RF_CPG = 15
Applies to both low and high
current modes
-200
-206
-208
-210
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
L
F1Hz
IF
IF Synthesizer Normalized
Phase Noise Contribution
(Note 3)
-209
dBc/Hz
Note 3:
Normalized Phase Noise Contribution is defined as: L
N
(f) = L(f) – 20log(N) – 10log(f
COMP
) where L(f) is defined as the single side band phase noise
measured at an offset frequency, f, in a 1 Hz Bandwidth. The offset frequency, f, must be chosen sufficiently smaller than the PLL loop bandwidth, yet large enough
to avoid substantial phase noise contribution from the reference source. The offset chosen was 4 KHz.
MICROWIRE INPUT TIMING DIAGRAM
20059372
L
www.national.com
5
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PDF描述 |
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| LMX2485 | 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL |
| LMX2485E | 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL |
| LMX2485ESQ | 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL |
| LMX2485ESQX | 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL |
| LMX2485SQ | 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LMX2470SLEX/NOPB | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類(lèi)型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| LMX2471 | 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:3.6 GHz Delta-Sigma Fractional-N PLL with 1.7 GHz Integer-N PLL |
| LMX2471 WAF | 制造商:Texas Instruments 功能描述: |
| LMX2471SLEX | 功能描述:IC PLL LP 3.6GHZ/1.7GHZ 24-CSP RoHS:否 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類(lèi)型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| LMX2471SLEX/NOPB | 制造商:Texas Instruments 功能描述:PLL Dual 250MHz to 3600MHz 24-Pin LAM CSP T/R |
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