參數(shù)資料
型號： LPC11U14FET48/201,
廠商： NXP Semiconductors
文件頁數(shù)： 71/72頁
文件大?。?/td> 0K
描述： IC MCU 32BIT 32K 48TFBGA
產(chǎn)品培訓(xùn)模塊： Code Density for LPC11xx
標(biāo)準(zhǔn)包裝： 490
系列： LPC11Uxx
核心處理器： ARM? Cortex?-M0
芯體尺寸： 32-位
速度： 50MHz
連通性： I²C，Microwire，智能卡，SPI，SSP，UART/USART，USB
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，WDT
輸入/輸出數(shù)： 40
程序存儲器容量： 32KB（32K x 8）
程序存儲器類型： 閃存
RAM 容量： 6K x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 48-TFBGA
包裝： 托盤
其它名稱： 568-8578
LPC11U1X
All information provided in this document is subject to legal disclaimers.
NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.2 — 11 March 2014
8 of 72
NXP Semiconductors
LPC11U1x
32-bit ARM Cortex-M0 microcontroller
6.2 Pin description
Table 3 shows all pins and their assigned digital or analog functions ordered by GPIO port
number. The default function after reset is listed first. All port pins have internal pull-up
resistors enabled after reset with the exception of the true open-drain pins PIO0_4 and
PIO0_5.
Every port pin has a corresponding IOCON register for programming the digital or analog
function, the pull-up/pull-down configuration, the repeater, and the open-drain modes.
The USART, counter/timer, and SSP functions are available on more than one port pin.
Table 4 shows how peripheral functions are assigned to port pins.
Table 3.
Pin description
Symbol
Pin
HVQFN3
3
Pi
n
LQ
F
P
4
8
Ba
ll
TFBGA4
8
Reset
state
Type
Description
RESET/PIO0_0
2
3
C1
I; PU
I
RESET — External reset input with 20 ns glitch
filter. A LOW-going pulse as short as 50 ns on
this pin resets the device, causing I/O ports and
peripherals to take on their default states, and
processor execution to begin at address 0. This
pin also serves as the debug select input. LOW
level selects the JTAG boundary scan. HIGH
level selects the ARM SWD debug mode.
In deep power-down mode, this pin must be
pulled HIGH externally. The RESET pin can be
left unconnected or be used as a GPIO pin if an
external RESET function is not needed and
Deep power-down mode is not used.
-I/O
PIO0_0 — General purpose digital input/output
pin.
PIO0_1/CLKOUT/
CT32B0_MAT2/
USB_FTOGGLE
34
C2
I; PU
I/O
PIO0_1 — General purpose digital input/output
pin. A LOW level on this pin during reset starts
the ISP command handler.
-O
CLKOUT — Clockout pin.
-O
CT32B0_MAT2 — Match output 2 for 32-bit
timer 0.
-O
USB_FTOGGLE — USB 1 ms Start-of-Frame
signal.
PIO0_2/SSEL0/
CT16B0_CAP0
810
F1
I; PU
I/O
PIO0_2 — General purpose digital input/output
pin.
-I/O
SSEL0 — Slave select for SSP0.
-I
CT16B0_CAP0 — Capture input 0 for 16-bit
timer 0.
PIO0_3/USB_VBUS
9
14
H2
I; PU
I/O
PIO0_3 — General purpose digital input/output
pin.
-I
USB_VBUS — Monitors the presence of USB
bus power.
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