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參數(shù)資料
| 型號： | LPC1313FHN33/01,55 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 17/74頁 |
| 文件大?。?/td> | 0K |
| 描述： | MCU CORTEX M3 32KB FLASH 32HVQFN |
| 標(biāo)準(zhǔn)包裝： | 260 |
| 系列： | LPC13xx |
| 核心處理器： | ARM? Cortex?-M3 |
| 芯體尺寸： | 32-位 |
| 速度： | 72MHz |
| 連通性： | I²C，Microwire，SPI，SSI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，POR，WDT |
| 輸入/輸出數(shù)： | 28 |
| 程序存儲器容量： | 32KB（32K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 8K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 32-VQFN 裸露焊盤 |
| 包裝： | 托盤 |
| 其它名稱： | 568-8375 |
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LPC1311_13_42_43
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 6 June 2012
24 of 74
NXP Semiconductors
LPC1311/13/42/43
32-bit ARM Cortex-M3 microcontroller
Selectable time period from (Tcy(WDCLK)
× 256 × 4) to (Tcy(WDCLK) × 224 × 4) in
multiples of Tcy(WDCLK)
× 4.
The Watchdog Clock (WDCLK) source can be selected from the Internal RC oscillator
(IRC), the watchdog oscillator, or the main clock. This gives a wide range of potential
timing choices of watchdog operation under different power reduction conditions. It
also provides the ability to run the WDT from an entirely internal source that is not
dependent on an external crystal and its associated components and wiring for
increased reliability.
7.17 Windowed WatchDog Timer (WWDT)
Remark: The windowed watchdog timer is available on parts LPC1311/01 and
LPC1313/01.
The purpose of the watchdog is to reset the controller if software fails to periodically
service it within a programmable time window.
7.17.1 Features
Internally resets chip if not periodically reloaded during the programmable time-out
period.
Optional windowed operation requires reload to occur between a minimum and
maximum time period, both programmable.
Optional warning interrupt can be generated at a programmable time prior to
watchdog time-out.
Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
Incorrect feed sequence causes reset or interrupt if enabled.
Flag to indicate watchdog reset.
Programmable 24-bit timer with internal prescaler.
Selectable time period from (Tcy(WDCLK)
× 256 × 4) to (Tcy(WDCLK) × 224 × 4) in
multiples of Tcy(WDCLK)
× 4.
The Watchdog Clock (WDCLK) source can be selected from the IRC or the dedicated
watchdog oscillator (WDO). This gives a wide range of potential timing choices of
watchdog operation under different power conditions.
7.18 Clocking and power control
7.18.1 Integrated oscillators
The LPC1311/13/42/43 include three independent oscillators. These are the system
oscillator, the Internal RC oscillator (IRC), and the watchdog oscillator. Each oscillator can
be used for more than one purpose as required in a particular application.
Following reset, the LPC1311/13/42/43 will operate from the internal RC oscillator until
switched by software. This allows systems to operate without any external crystal and the
bootloader code to operate at a known frequency.
See Figure 7 for an overview of the LPC1311/13/42/43 clock generation.
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