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參數(shù)資料
| 型號(hào)： | LPC1313FHN33/01,55 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 5/74頁 |
| 文件大?。?/td> | 0K |
| 描述： | MCU CORTEX M3 32KB FLASH 32HVQFN |
| 標(biāo)準(zhǔn)包裝： | 260 |
| 系列： | LPC13xx |
| 核心處理器： | ARM? Cortex?-M3 |
| 芯體尺寸： | 32-位 |
| 速度： | 72MHz |
| 連通性： | I²C，Microwire，SPI，SSI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測(cè)/復(fù)位，POR，WDT |
| 輸入/輸出數(shù)： | 28 |
| 程序存儲(chǔ)器容量： | 32KB（32K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 8K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 32-VQFN 裸露焊盤 |
| 包裝： | 托盤 |
| 其它名稱： | 568-8375 |
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LPC1311_13_42_43
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 6 June 2012
13 of 74
NXP Semiconductors
LPC1311/13/42/43
32-bit ARM Cortex-M3 microcontroller
[1]
Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (for VDD = 3.3 V, pin is pulled up to 2.6 V for
parts LPC1311/13/42/43 and pulled up to 3.3 V for parts LPC1311/01 and LPC1313/01); IA = inactive, no pull-up/down enabled;
F = floating; floating pins, if not used, should be tied to ground or power to minimize power consumption.
[2]
5 V tolerant pad. See Figure 37 for pad characteristics. RESET functionality is not available in Deep power-down mode. Use the
WAKEUP pin to reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the
Deep power-down mode.
[3]
5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 36).
[4]
I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus.
[5]
5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.
When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 36).
[6]
Pad provides USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode
only). This pad is not 5 V tolerant.
[7]
When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded
(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.
PIO2_10
25[3] yes
I/O
I; PU
PIO2_10 — General purpose digital input/output pin.
PIO2_11/SCK0
31[3] yes
I/O
I; PU
PIO2_11 — General purpose digital input/output pin.
I/O
-
SCK0 — Serial clock for SSP0.
PIO3_0/DTR
36[3] yes
I/O
I; PU
PIO3_0 — General purpose digital input/output pin.
O-
DTR — Data Terminal Ready output for UART (LPC1311/01 and
LPC1313/01 only).
PIO3_1/DSR
37[3] yes
I/O
I; PU
PIO3_1 — General purpose digital input/output pin.
I-
DSR — Data Set Ready input for UART (LPC1311/01 and
LPC1313/01 only).
PIO3_2/DCD
43[3] yes
I/O
I; PU
PIO3_2 — General purpose digital input/output pin.
I-
DCD — Data Carrier Detect input for UART (LPC1311/01 and
LPC1313/01 only).
PIO3_3/RI
48[3] yes
I/O
I; PU
PIO3_3 — General purpose digital input/output pin.
I-
RI — Ring Indicator input for UART (LPC1311/01 and LPC1313/01
only).
PIO3_4
18[3] no
I/O
I; PU
PIO3_4 — General purpose digital input/output pin (LPC1313 only).
PIO3_5
21[3] no
I/O
I; PU
PIO3_5 — General purpose digital input/output pin (LPC1313 only).
USB_DM
19[6] no
I/O
F
USB_DM — USB bidirectional D
line (LPC1342/43 only).
USB_DP
20[6] no
I/O
F
USB_DP — USB bidirectional D+ line (LPC1342/43 only).
VDD
8;
44
-
I
-
3.3 V supply voltage to the internal regulator, the external rail, and
the ADC. Also used as the ADC reference voltage.
XTALIN
6[7]
-
I
-
Input to the oscillator circuit and internal clock generator circuits.
Input voltage must not exceed 1.8 V.
XTALOUT
7[7]
-
O
-
Output from the oscillator amplifier.
VSS
5;
41
-
I
-
Ground.
Table 3.
LPC1313/42/43 LQFP48 pin description table …continued
Symbol
Pin
Start
logic
input
Type Reset
state
[1]
Description
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