參數(shù)資料
型號(hào)： LPC2106
廠商： NXP Semiconductors N.V.
英文描述： Single-chip 32-bit microcontrollers; 128 kB ISP/IAP Flash with 64 kB/32 kB/16 kB RAM
中文描述： 單片32位微控制器，128 kB的供應(yīng)商/聯(lián)合會(huì)64 kB/32 kB/16 KB RAM內(nèi)存閃存
文件頁(yè)數(shù)： 12/32頁(yè)
文件大?。?/td> 155K
代理商： LPC2106
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Product data
Rev. 04 — 05 February 2004
12 of 32
9397 750 12792
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be
assigned to this category. Any of the interrupt requests can be assigned to any of the
16 vectored IRQ slots, among which slot 0 has the highest priority and slot 15 has the
lowest.
Non-vectored IRQs have the lowest priority.
The VIC combines the requests from all the vectored and non-vectored IRQs to
produce the IRQ signal to the ARM processor. The IRQ service routine can start by
reading a register from the VIC and jumping there. If any of the vectored IRQs are
requesting, the VIC provides the address of the highest-priority requesting IRQs
service routine, otherwise it provides the address of a default routine that is shared by
all the non-vectored IRQs. The default routine can read another VIC register to see
what IRQs are active.
6.5.1
Interrupt sources
Table 4
lists the interrupt sources for each peripheral function. Each peripheral device
has one interrupt line connected to the Vectored Interrupt Controller, but may have
several internal interrupt flags. Individual interrupt flags may also represent more than
one interrupt source.
Table 4:
Block
WDT
-
ARM Core
ARM Core
Timer 0
Interrupt sources
Flag(s)
Watchdog Interrupt (WDINT)
Reserved for software interrupts only
Embedded ICE, DbgCommRx
Embedded ICE, DbgCommTx
Match 0 - 3 (MR0, MR1, MR2, MR3)
Capture 0 - 3 (CR0, CR1, CR2, CR3)
Match 0 - 3 (MR0, MR1, MR2, MR3)
Capture 0 - 3 (CR0, CR1, CR2, CR3)
Rx Line Status (RLS)
Transmit Holding Register empty (THRE)
Rx Data Available (RDA)
Character Time-out Indicator (CTI)
Rx Line Status (RLS)
Transmit Holding Register empty (THRE)
Rx Data Available (RDA)
Character Time-out Indicator (CTI)
Modem Status Interrupt (MSI)
Match 0 - 6 (MR0, MR1, MR2, MR3, MR4, MR5, MR6)
SI (state change)
SPIF, MODF
reserved
PLL Lock (PLOCK)
RTCCIF (Counter Increment), RTCALF (Alarm)
VIC channel #
0
1
2
3
4
Timer 1
5
UART 0
6
UART 1
7
PWM0
I
2
C
SPI
-
PLL
RTC
8
9
10
11
12
13
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