參數(shù)資料
型號(hào)： LPC2106
廠商： NXP Semiconductors N.V.
英文描述： Single-chip 32-bit microcontrollers; 128 kB ISP/IAP Flash with 64 kB/32 kB/16 kB RAM
中文描述： 單片32位微控制器，128 kB的供應(yīng)商/聯(lián)合會(huì)64 kB/32 kB/16 KB RAM內(nèi)存閃存
文件頁(yè)數(shù)： 21/32頁(yè)
文件大?。?/td> 155K
代理商： LPC2106
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Product data
Rev. 04 — 05 February 2004
21 of 32
9397 750 12792
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
6.17.4
External interrupt inputs
The LPC2104, LPC2105 and LPC2106 include three External Interrupt Inputs as
selectable pin functions. The External Interrupt Inputs can optionally be used to wake
up the processor from Power-down mode.
6.17.5
Memory Mapping Control
The Memory Mapping Control alters the mapping of the interrupt vectors that appear
beginning at address 0x00000000. Vectors may be mapped to the bottom of the
on-chip Flash memory, or to the on-chip static RAM. This allows code running in
different memory spaces to have control of the interrupts.
6.17.6
Power Control
The LPC2104, LPC2105 and LPC2106 support two reduced power modes: Idle
mode and Power-down mode. In Idle mode, execution of instructions is suspended
until either a Reset or interrupt occurs. Peripheral functions continue operation during
Idle mode and may generate interrupts to cause the processor to resume execution.
Idle mode eliminates power used by the processor itself, memory systems and
related controllers, and internal buses.
In Power-down mode, the oscillator is shut down and the chip receives no internal
clocks. The processor state and registers, peripheral registers, and internal SRAM
values are preserved throughout Power-down mode and the logic levels of chip
output pins remain static. The Power-down mode can be terminated and normal
operation resumed by either a Reset or certain specific interrupts that are able to
function without clocks. Since all dynamic operation of the chip is suspended,
Power-down mode reduces chip power consumption to nearly zero.
A Power Control for Peripherals feature allows individual peripherals to be turned off if
they are not needed in the application, resulting in additional power savings.
6.17.7
VPB bus
The VPB Divider determines the relationship between the processor clock (cclk) and
the clock used by peripheral devices (PCLK). The VPB Divider serves two purposes.
The first is that the VPB bus cannot operate at the highest speeds of the CPU. In
order to compensate for this, the VPB bus may be slowed down to one half or one
fourth of the processor clock rate. The default condition at reset is for the VPB bus to
run at one quarter of the CPU clock. The second purpose of the VPB Divider is to
allow power savings when an application does not require any peripherals to run at
the full processor rate. Because the VPB Divider is connected to the PLL output, the
PLL remains active (if it was running) during Idle mode.
6.18 Emulation and debugging
The LPC2104, LPC2105 and LPC2106 support emulation and debugging via a JTAG
serial port. A trace port allows tracing program execution. Each of these functions
requires a trade-off of debugging features versus device pins. Because the LPC2104,
LPC2105 and LPC2106 are provided in a small package, there is no room for
permanently assigned JTAG or Trace pins. An alternate JTAG port allows an option to
debug functions assigned to the pins used by the primary JTAG port.
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