參數(shù)資料
型號(hào)： LPC2106
廠商： NXP Semiconductors N.V.
英文描述： Single-chip 32-bit microcontrollers; 128 kB ISP/IAP Flash with 64 kB/32 kB/16 kB RAM
中文描述： 單片32位微控制器，128 kB的供應(yīng)商/聯(lián)合會(huì)64 kB/32 kB/16 KB RAM內(nèi)存閃存
文件頁(yè)數(shù)： 16/32頁(yè)
文件大小： 155K
代理商： LPC2106
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Product data
Rev. 04 — 05 February 2004
16 of 32
9397 750 12792
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
6.10 UARTs
The LPC2104, LPC2105 and LPC2106 each contain two UARTs. One UART
provides a full modem control handshake interface, the other provides only transmit
and receive data lines.
6.10.1
Features
16 byte Receive and Transmit FIFOs.
Register locations conform to ‘550 industry standard.
Receiver FIFO trigger points at 1, 4, 8, and 14 bytes
Built-in baud rate generator.
Standard modem interface signals included on UART 1.
6.11 I
2
C serial I/O controller
I
2
C is a bi-directional bus for inter-IC control using only two wires: a serial clock line
(SCL), and a serial data line (SDA). Each device is recognized by a unique address
and can operate as either a receiver-only device (e.g. an LCD driver or a transmitter
with the capability to both receive and send information (such as memory).
Transmitters and/or receivers can operate in either master or slave mode, depending
on whether the chip has to initiate a data transfer or is only addressed. I
2
C is a
multi-master bus, it can be controlled by more than one bus master connected to it.
I
2
C implemented in LPC2104, LPC2105 and LPC2106 supports bit rate up to
400 kbit/s (Fast I
2
C).
6.11.1
Features
Standard I
2
C compliant bus interface.
Easy to configure as Master, Slave, or Master/Slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of
serial data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate
via one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend
and resume serial transfer.
The I
2
C bus may be used for test and diagnostic purposes.
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