參數(shù)資料
型號(hào): LPC2106BBD48
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Single-chip 32-bit microcontrollers; 128 kB ISP/IAP Flash with 64 kB/32 kB/16 kB RAM
中文描述: 32-BIT, FLASH, 60 MHz, RISC MICROCONTROLLER, PQFP48
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT313-2, LQFP-48
文件頁(yè)數(shù): 17/32頁(yè)
文件大小: 155K
代理商: LPC2106BBD48
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Product data
Rev. 04 — 05 February 2004
17 of 32
9397 750 12792
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
6.12 SPI serial I/O controller
The SPI is a full duplex serial interface, designed to be able to handle multiple
masters and slaves connected to a given bus. Only a single master and a single slave
can communicate on the interface during a given data transfer. During a data transfer
the master always sends a byte of data to the slave, and the slave always sends a
byte of data to the master.
6.12.1
Features
Compliant with Serial Peripheral Interface (SPI) specification.
Synchronous, Serial, Full Duplex, Communication.
Combined SPI master and slave.
Maximum data bit rate of one eighth of the input clock rate.
6.13 General purpose timers
The Timer is designed to count cycles of the peripheral clock (PCLK) and optionally
generate interrupts or perform other actions at specified timer values, based on four
match registers. It also includes four capture inputs to trap the timer value when an
input signal transitions, optionally generating an interrupt.
6.13.1
Features
A 32-bit Timer/Counter with a programmable 32-bit Prescaler.
Up to four (TImer 1) and three (Timer 0) 32-bit capture channels, that can take a
snapshot of the timer value when an input signal transitions. A capture event may
also optionally generate an interrupt.
Four 32-bit match registers that allow:
Continuous operation with optional interrupt generation on match.
Stop timer on match with optional interrupt generation.
Reset timer on match with optional interrupt generation.
Up to four (Timer 1) and three (Timer 0) external outputs corresponding to match
registers, with the following capabilities:
Set LOW on match.
Set HIGH on match.
Toggle on match.
Do nothing on match.
6.14 Watchdog timer
The purpose of the Watchdog is to reset the microcontroller within a reasonable
amount of time if it enters an erroneous state. When enabled, the Watchdog will
generate a system reset if the user program fails to ‘feed’ (or reload) the Watchdog
within a predetermined amount of time.
相關(guān)PDF資料
PDF描述
LPC2104 Single-chip 32-bit microcontrollers; 128 kB ISP/IAP Flash with 64 kB/32 kB/16 kB RAM
LPC2105 Single-chip 32-bit microcontrollers; 128 kB ISP/IAP Flash with 64 kB/32 kB/16 kB RAM
LPC2106 Single-chip 32-bit microcontrollers; 128 kB ISP/IAP Flash with 64 kB/32 kB/16 kB RAM
LPC2119 CLAMP
LPC2129 SPACER
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