參數(shù)資料
型號: LPC2106BBD48
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Single-chip 32-bit microcontrollers; 128 kB ISP/IAP Flash with 64 kB/32 kB/16 kB RAM
中文描述: 32-BIT, FLASH, 60 MHz, RISC MICROCONTROLLER, PQFP48
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT313-2, LQFP-48
文件頁數(shù): 7/32頁
文件大?。?/td> 155K
代理商: LPC2106BBD48
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Product data
Rev. 04 — 05 February 2004
7 of 32
9397 750 12792
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
33
I/O
O
I/O
O
I/O
O
I/O
O
P0.23 —
Port 0 bit 23.
PIPESTAT0 —
Pipeline Status, bit 0. Standard I/O port with internal pull-up.
P0.24 —
Port 0 bit 24.
PIPESTAT1 —
Pipeline Status, bit 1. Standard I/O port with internal pull-up.
P0.25 —
Port 0 bit 25.
PIPESTAT2 —
Pipeline Status, bit 2. Standard I/O port with internal pull-up.
P0.26 —
Port 0 bit 26.
TRACESYNC —
Trace Synchronization Standard I/O port with internal
pull-up.
P0.27 —
Port 0 bit 27.
TRACEPKT0 —
Trace Packet, bit 0. Standard I/O port with internal pull-up.
TRST —
Test Reset for JTAG interface, secondary JTAG pin group.
P0.28 —
Port 0 bit 28.
TRACEPKT1 —
Trace Packet, bit 1. Standard I/O port with internal pull-up.
TMS —
Test Mode Select for JTAG interface, secondary JTAG pin group
P0.29 —
Port 0 bit 29.
TRACEPKT2 —
Trace Packet, bit 2. Standard I/O port with internal pull-up.
TCK —
Test Clock for JTAG interface, secondary JTAG pin group.
P0.30 —
Port 0 bit 30.
TRACEPKT3 —
Trace Packet, bit 3. Standard I/O port with internal pull-up.
TDI —
Test Data In for JTAG interface, secondary JTAG pin group.
P0.31 —
Port 0 bit 31.
EXTIN0 —
External Trigger Input. Standard I/O port with internal pull-up.
TDO —
Test Data out for JTAG interface, secondary JTAG pin group.
Returned Test Clock output:
Extra signal added to the JTAG port. Assists
debugger synchronization when processor frequency varies. Also used
during debug mode entry to select primary or secondary JTAG pins with the
48-pin package. Bi-directional pin with internal pull-up.
Debug Select:
When LOW, the part operates normally. When HIGH, debug
mode is entered. Input pin with internal pull-down.
External Reset input:
A LOW on this pin resets the device, causing I/O ports
and peripherals to take on their default states, and processor execution to
begin at address 0.
Input to the oscillator circuit and internal clock generator circuits.
Output from the oscillator amplifier.
Ground:
0 V reference.
1.8 V Core Power Supply:
This is the power supply voltage for internal
circuitry.
3.3 V Pad Power Supply:
This is the power supply voltage for the I/O ports.
Not Connected:
These pins are not connected in the 48 pin package.
34
38
39
8
I/O
O
I
I/O
O
I
I/O
O
I
I/O
O
I
I/O
I
O
I/O
9
10
15
16
RTCK
26
DBGSEL
27
I
RST
6
I
X1
X2
V
SS1
- V
SS4
V
DD1.8
11
12
7, 19, 31, 43
5
I
O
I
I
V
DD3
NC
17, 40
4, 20, 25, 42
I
-
Table 3:
Symbol
Pin description
…continued
Pin
Type
Description
相關(guān)PDF資料
PDF描述
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