參數(shù)資料
型號: LPC2388FBD144
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學處理器
英文描述: Single-chip 16-bit-32-bit micro; 512 kB flash with ISP-IAP, Ethernet, USB 2.0 device-host-OTG, CAN, and 10-bit ADC-DAC
封裝: LPC2388FBD144<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.html<1<Always Pb-free,;
文件頁數(shù): 34/72頁
文件大?。?/td> 1469K
代理商: LPC2388FBD144
LPC2388
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 13 July 2010
34 of 72
NXP Semiconductors
LPC2388
Single-chip 16-bit/32-bit microcontroller
7.25.4.5
Power domains
The LPC2388 provides two independent power domains that allow the bulk of the device
to have power removed while maintaining operation of the RTC and the battery RAM.
On the LPC2388, I/O pads are powered by the 3.3 V (V
DD(3V3)
) pins, while the
V
DD(DCDC)(3V3)
pin powers the on-chip DC-to-DC converter which in turn provides power to
the CPU and most of the peripherals.
Depending on the LPC2388 application, a design can use two power options to manage
power consumption.
The first option assumes that power consumption is not a concern and the design ties the
V
DD(3V3)
and V
DD(DCDC)(3V3)
pins together. This approach requires only one 3.3 V power
supply for both pads, the CPU, and peripherals. While this solution is simple, it does not
support powering down the I/O pad ring “on the fly” while keeping the CPU and
peripherals alive.
The second option uses two power supplies; a 3.3 V supply for the I/O pads (V
DD(3V3)
) and
a dedicated 3.3 V supply for the CPU (V
DD(DCDC)(3V3)
). Having the on-chip DC-to-DC
converter powered independently from the I/O pad ring enables shutting down of the I/O
pad power supply “on the fly”, while the CPU and peripherals stay active.
The VBAT pin supplies power only to the RTC and the battery RAM. These two functions
require a minimum of power to operate, which can be supplied by an external battery.
When the CPU and the rest of chip functions are stopped and power removed, the RTC
can supply an alarm output that may be used by external hardware to restore chip power
and resume operation.
7.26 System control
7.26.1
Reset
Reset has four sources on the LPC2388: the RESET pin, the Watchdog reset, power-on
reset, and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input
pin. Assertion of chip Reset by any source, once the operating voltage attains a usable
level, starts the Wake-up timer (see description in
Section 7.25.3 “Wake-up timer”
),
causing reset to remain asserted until the external Reset is de-asserted, the oscillator is
running, a fixed number of clocks have passed, and the flash controller has completed its
initialization.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the Boot Block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
7.26.2
Brownout detection
The LPC2388 includes 2-stage monitoring of the voltage on the V
DD(DCDC)(3V3)
pins. If this
voltage falls below 2.95 V, the BOD asserts an interrupt signal to the VIC. This signal can
be enabled for interrupt in the Interrupt Enable Register in the VIC in order to cause a
CPU interrupt; if not, software can monitor the signal by reading a dedicated status
register.
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