參數(shù)資料
型號(hào): LPC2470
廠商: NXP Semiconductors N.V.
英文描述: Flashless 16-bit/32-bit micro; Ethernet, CAN, LCD, USB 2.0 device/host/OTG, external memory interface
中文描述: 毛邊16-bit/32-bit微,以太網(wǎng),CAN,液晶顯示器,USB 2.0設(shè)備/主機(jī)/ OTG功能,外部存儲(chǔ)器接口
文件頁(yè)數(shù): 31/72頁(yè)
文件大?。?/td> 365K
代理商: LPC2470
LPC2470_0
NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 00.01 — 5 October 2007
31 of 72
NXP Semiconductors
LPC2470
Fast communication chip
32-bit AHB master bus width.
Incrementing or non-incrementing addressing for source and destination.
Programmable DMA burst size. The DMA burst size can be programmed to more
efficiently transfer data. Usually the burst size is set to half the size of the FIFO in the
peripheral.
Internal four-word FIFO per channel.
Supports 8-bit, 16-bit, and 32-bit wide transactions.
An interrupt to the processor can be generated on a DMA completion or when a DMA
error has occurred.
Interrupt masking. The DMA error and DMA terminal count interrupt requests can be
masked.
Raw interrupt status. The DMA error and DMA count raw interrupt status can be read
prior to masking.
7.8 Fast general purpose parallel I/O
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate
registers allow setting or clearing any number of outputs simultaneously. The value of the
output register may be read back as well as the current state of the port pins.
LPC2470 use accelerated GPIO functions:
GPIO registers are relocated to the ARM local bus so that the fastest possible I/O
timing can be achieved.
Mask registers allow treating sets of port bits as a group, leaving other bits
unchanged.
All GPIO registers are byte and half-word addressable.
Entire port value can be written in one instruction.
Additionally, any pin on PORT0 and PORT2 (total of 64 pins) that is not configured as an
analog input/output can be programmed to generate an interrupt on a rising edge, a falling
edge, or both. The edge detection is asynchronous, so it may operate when clocks are not
present such as during Power-down mode. Each enabled interrupt can be used to wake
the chip up from Power-down mode.
7.8.1
Features
Bit level set and clear registers allow a single instruction to set or clear any number of
bits in one port.
Direction control of individual bits.
All I/O default to inputs after reset.
Backward compatibility with other earlier devices is maintained with legacy PORT0
and PORT1 registers appearing at the original addresses on the APB bus.
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