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參數(shù)資料
| 型號： | LPC3250FET296/01,5 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 27/57頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ARM9 MCU 256K 296-TFBGA |
| 標準包裝： | 126 |
| 系列： | LPC3200 |
| 核心處理器： | ARM9 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 266MHz |
| 連通性： | EBI/EMI，以太網(wǎng)，I²C，IrDA，Microwire，SPI，SSI，SSP，UART/USART，USB OTG |
| 外圍設備： | DMA，I²S，LCD，電機控制 PWM，PWM，WDT |
| 輸入/輸出數(shù)： | 51 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 256K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 0.9 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 3x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 296-TFBGA |
| 包裝： | 托盤 |
| 其它名稱： | 568-4962 935290766551 |
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LPC3220_30_40_50
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 20 October 2011
33 of 79
NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
Supports Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) for
dual-role devices under software control. HNP is partially implemented in hardware.
Provides programmable timers required for HNP and SRP.
Supports slave mode operation through AHB slave interface.
Supports the OTG ATX from NXP (ISP 1302) or any external CEA-2011OTG
specification compliant ATX.
7.6.4 LCD controller
The LCD controller provides all of the necessary control signals to interface directly to a
variety of color and monochrome LCD panels. Both STN (single and dual panel) and TFT
panels can be operated. The display resolution is selectable and can be up to 1024
768
pixels. Several color modes are provided, up to a 24-bit true-color non-palettized mode.
An on-chip 512-byte color palette allows reducing bus utilization (i.e. memory size of the
displayed data) while still supporting a large number of colors.
The LCD interface includes its own DMA controller to allow it to operate independently of
the CPU and other system functions. A built-in FIFO acts as a buffer for display data,
providing flexibility for system timing. Hardware cursor support can further reduce the
amount of CPU time needed to operate the display.
7.6.4.1
Features
AHB bus master interface to access frame buffer.
Setup and control via a separate AHB slave interface.
Dual 16-deep programmable 64-bit wide FIFOs for buffering incoming display data.
Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays
with 4-bit or 8-bit interfaces.
Supports single and dual-panel color STN displays.
Supports Thin Film Transistor (TFT) color displays.
Programmable display resolution including, but not limited to: 320 200, 320 240,
640
200, 640 240, 640 480, 800 600, and 1024 768.
Hardware cursor support for single-panel displays.
15 gray-level monochrome, 3375 color STN, and 32 k color palettized TFT support.
1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome STN.
1, 2, 4, or 8 bpp palettized color displays for color STN and TFT.
16 bpp true-color non-palettized, for color STN and TFT.
24 bpp true-color non-palettized, for color TFT.
Programmable timing for different display panels.
256 entry, 16-bit palette RAM, arranged as a 128 32 bit RAM.
Frame, line, and pixel clock signals.
AC bias signal for STN, data enable signal for TFT panels.
Supports little and big-endian, and Windows CE data formats.
LCD panel clock may be generated from the peripheral clock or from a clock input pin.
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