參數(shù)資料
型號： LPC3250FET296/01,5
廠商： NXP Semiconductors
文件頁數(shù)： 31/57頁
文件大?。?/td> 0K
描述： IC ARM9 MCU 256K 296-TFBGA
標(biāo)準包裝： 126
系列： LPC3200
核心處理器： ARM9
芯體尺寸： 16/32-位
速度： 266MHz
連通性： EBI/EMI，以太網(wǎng)，I²C，IrDA，Microwire，SPI，SSI，SSP，UART/USART，USB OTG
外圍設(shè)備： DMA，I²S，LCD，電機控制 PWM，PWM，WDT
輸入/輸出數(shù)： 51
程序存儲器類型： ROMless
RAM 容量： 256K x 8
電壓 - 電源 (Vcc/Vdd)： 0.9 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 3x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 296-TFBGA
包裝： 托盤
其它名稱： 568-4962
935290766551
LPC3220_30_40_50
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 20 October 2011
37 of 79
NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
7.8.1 UARTs
The LPC3220/30/40/50 contains seven UARTs. Four are standard UARTs, and three are
high-speed UARTs.
7.8.1.1
Standard UARTs
The four standard UARTs are compatible with the INS16Cx50. These UARTs support
rates up to 460800 bit/s from a 13 MHz peripheral clock.
Features
Each standard UART has 64 byte Receive and Transmit FIFOs.
Receiver FIFO trigger points at 16, 32, 48, and 60 Bytes.
Transmitter FIFO trigger points at 0, 4, 8, and 16 Bytes.
Register locations conform to the “550” industry standard.
Each standard UART has a fractional rate pre-divider and an internal baud rate
generator.
The standard UARTs support three clocking modes: on, off, and auto-clock. The
auto-clock mode shuts off the clock to the UART when it is idle.
UART 6 includes an IrDA mode to support infrared communication.
The standard UARTs are designed to support data rates of (2400, 4800, 9600,
19200, 38400, 57600, 115200, 230400, 460800) bit/s.
Each UART includes an internal loopback mode.
7.8.1.2
High-speed UARTs
The three high-speed UARTs are designed to support rates up to 921600 bit/s from a
13 MHz peripheral clock for on-board communication in low noise conditions. This is
accomplished by changing the over sampling from 16
to 14 and altering the rate
generation logic.
Features
Each high-speed UART has 64-byte Receive and Transmit FIFOs.
Receiver FIFO trigger points at 1, 4, 8, 16, 32, and 48 B.
Transmitter FIFO trigger points at 0, 4, and 8 B.
Each high-speed UART has an internal baud rate generator.
The high-speed UARTs are designed to support data rates of (2400, 4800, 9600,
19200, 38400, 57600, 115200, 230400, 460800, 921600) bit/s.
The three high speed UARTs only support (8N1) 8-bit data word length, 1-stop bit, no
parity, and no flow control as a the communications protocol.
Each UART includes an internal loopback mode.
7.8.2 SPI serial I/O controller
The LPC3220/30/40/50 has two Serial Peripheral Interfaces (SPI). The SPI is a 3-wire
serial interface that is able to interface with a large range of serial peripheral or memory
devices (SPI mode 0 to 3 compatible slave devices).
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