參數(shù)資料
型號(hào)： LRS1311
英文描述： SRAM/EEPROM
中文描述： 的SRAM / EEPROM的
文件頁(yè)數(shù)： 10/43頁(yè)
文件大小： 1326K
代理商： LRS1311
LRS1382
8
5. Command Definitions for Flash Memory
(11)
5.1 Command Definitions
Notes:
1. Bus operations are defined in 3.1 Bus Operation.
2. All addresses which are written at the first bus cycle should be the same as the addresses which are written at the second
bus cycle.
X=Any valid address within the device.
PA=Address within the selected partition.
IA=Identifier codes address (See 5.2 Identifier Codes for Read Operation).
QA=Query codes address. Refer to the LH28F320BF, LH28F640BF, LH28F128BF series Appendix for details.
BA=Address within the block being erased, set/cleared block lock bit or set block lock-down bit.
WA=Address of memory location for the Program command or the first address for the Page Buffer Program command.
PCRC=Partition configuration register code presented on the address A
0
-A
15
.
3. ID=Data read from identifier codes (See 5.2 Identifier Codes for Read Operation).
QD=Data read from query database. Refer to the LH28F320BF, LH28F640BF, LH28F128BF series Appendix for details.
SRD=Data read from status register. See 6. Status Register Definition for a description of the status register bits.
WD=
Data to be programmed at location WA. Data is latched on the rising edge of F-WE or F-CE (whichever goes high first)
during command write cycles.
N-1=N is the number of the words to be loaded into a page buffer.
4. Following the Read Identifier Codes command, read operations access manufacturer code, device code, block lock
configuration code, partition configuration register code (See 5.2 Identifier Codes for Read Operation).
The Read Query command is available for reading CFI (Common Flash Interface) information.
5. Block erase, full chip erase or (page buffer) program cannot be executed when the selected block is locked. Unlocked
block can be erased or programmed when F-RST is V
IH
.
6. Either 40H or 10H are recognized by the CUI (Command User Interface) as the program setup.
7. Following the third bus cycle, input the program sequential address and write data of “N” times. Finally, input the any
valid address within the target block to be programmed and the confirm command (D0H). Refer to the LH28F320BF,
LH28F640BF, LH28F128BF series Appendix for details.
Command
Bus
Cycles
Req’d
1
≥
2
≥
2
2
1
2
2
Notes
First Bus Cycle
Second Bus Cycle
Oper
(1)
Address
(2)
Data
Oper
(1)
Address
(2)
Data
(3)
Read Array
Read Identifier Codes
Read Query
Read Status Register
Clear Status Register
Block Erase
Full Chip Erase
Write
Write
Write
Write
Write
Write
Write
PA
PA
PA
PA
PA
BA
X
FFH
90H
98H
70H
50H
20H
30H
40H or
10H
E8H
4
4
Read
Read
Read
IA
QA
PA
ID
QD
SRD
5
Write
Write
BA
X
D0H
D0H
5,9
Program
2
5,6
Write
WA
Write
WA
WD
Page Buffer Program
Block Erase and (Page Buffer)
Program Suspend
Block Erase and (Page Buffer)
Program Resume
Set Block Lock Bit
Clear Block Lock Bit
Set Block Lock-down Bit
Set Partition Configuration
Register
≥
4
5,7
Write
WA
Write
WA
N-1
1
8,9
Write
PA
B0H
1
8,9
Write
PA
D0H
2
2
2
Write
Write
Write
BA
BA
BA
60H
60H
60H
Write
Write
Write
BA
BA
BA
01H
D0H
2FH
10
2
Write
PCRC
60H
Write
PCRC
04H
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