參數(shù)資料
型號(hào): LRS1311
英文描述: SRAM/EEPROM
中文描述: 的SRAM / EEPROM的
文件頁(yè)數(shù): 6/43頁(yè)
文件大小: 1326K
代理商: LRS1311
LRS1382
4
Pin
Description
Type
A
0
to A
16
, A
18
F-A
17
,
F-A
19
, F-A
20
S-A
17
F-CE
S-CE
1
, S-CE
2
F-WE
S-WE
F-OE
Address Inputs (Common)
Input
Address Inputs (Flash)
Input
Address Input (SRAM)
Input
Chip Enable Input (Flash)
Input
Chip Enable Inputs (SRAM)
Input
Write Enable Input (Flash)
Write Enable Input (SRAM)
Output Enable Input (Flash)
Input
Input
Input
S-OE
Output Enable Input (SRAM)
SRAM Byte Enable Input (DQ
0
to DQ
7
)
SRAM Byte Enable Input (DQ
8
to DQ
15
)
Reset Power Down Input (Flash)
Block erase and Write : V
IH
Read : V
IH
Reset Power Down : V
IL
Write Protect Input (Flash)
When F-WP is V
IL
, locked-down blocks cannot be unlocked. Erase or
program operation can be executed to the blocks which are not locked and
locked-down. When F-WP is V
IH
, lock-down is disabled.
Ready/Busy Output (Flash)
During an Erase or Write operation : V
OL
Block Erase and Write Suspend : High-Z (High impedance)
Input
S-LB
Input
S-UB
Input
F-RST
Input
F-WP
Input
F-RY/BY
Open Drain
Output
DQ
0
to DQ
15
F-V
CC
S-V
CC
Data Inputs and Outputs (Common)
Input / Output
Power Supply (Flash)
Power
Power Supply (SRAM)
Power
F-V
PP
Monitoring Power Supply Voltage (Flash)
Block Erase and Write : F-V
PP
= V
PPH1/2
All Blocks Locked : F-V
PP
< V
PPLK
GND (Common)
Input
GND
Power
NC
Non Connection
-
T
1
to T
3
Test pins (Should be all open)
-
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LRS1320A 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:SRAM/EEPROM
LRS1329 制造商:SHARP 制造商全稱(chēng):Sharp Electrionic Components 功能描述:Stacked Chip 16M Flash and 2M SRAM
LRS1329A 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:MIXED MEMORY|SRAM+EEPROM|HYBRID|BGA|72PIN|PLASTIC
LRS1331 制造商:Sharp Microelectronics Corporation 功能描述:COMBO 1MX16 FLASH + 256KX16 SRAM 2.7V TO 3.6V 72FBGA - Trays
LRS1337 制造商:Sharp Microelectronics Corporation 功能描述:32M (2MX16) FLASH, 4M (256KX16) SRAM, 3V, CSP72 - Trays