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參數(shù)資料
| 型號： | LRS1338A |
| 廠商： | Sharp Corporation |
| 英文描述： | Stacked Chip 8M Flash Memory and 2M SRAM |
| 中文描述： | 堆疊芯片800萬快閃記憶體以及2M SRAM |
| 文件頁數(shù)： | 3/36頁 |
| 文件大?。?/td> | 218K |
| 代理商： | LRS1338A |
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Stacked Chip (8M Flash & 2M SRAM)
LRS1338A
Data Sheet
3
GENERAL DESIGN GUIDELINES
Supply Power
Maximum difference (between F-V
CC
and S-V
CC
) of
the voltage is less than 0.3 V.
Power Supply and Chip Enable of Flash
Memory and SRAM
It is forbidden that both F-CE and S-CE should be
LOW simultaneously. If the two memories are active
together, they many not operate normally due to inter-
ference noises or data collision on I/O bus. Both F-V
CC
and S-V
CC
need to be applied by the recommended
supply voltage at the same time except SRAM data
retention mode.
SRAM Data Retention
SRAM data retention is capable in three ways.
SRAM power switching between a system battery and
a backup battery needs careful device decoupling from
Flash Memory to prevent SRAM supply voltage from
falling lower than 2.0 V by a Flash Memory peak cur-
rent caused by transition of Flash Memory supply volt-
age or of control signals (F-CE, F-OE, and RP).
CASE 1: FLASH MEMORY IS IN STANDBY MODE
(F-V
CC
= 2.7 V TO 3.6 V)
SRAM inputs and input/outputs except S-CE need to
be applied with voltages in the range of -0.3 V to
S-V
CC
+ 0.3 V or to be open (HIGH-Z).
Flash Memory inputs and input/outputs except F-CE
and RP need to be applied with voltages in the range
of -0.3 V to S-V
CC
+ 0.3 V or to be open (HIGH-Z).
CASE 2: FLASH MEMORY IS IN DEEP POWER
DOWN MODE (F-V
CC
= 2.7 V TO 3.6 V)
SRAM inputs and input/outputs except S-CE need to
be applied with voltages in the range of -0.3 V to
S-V
CC
+ 0.3 V or to be open.
Flash Memory inputs and input/outputs except RP
need to be applied with voltages in the range of -0.3 V
to S-V
CC
+ 0.3 V or to be open (HIGH-Z). RP needs to
be at the same level as F-V
CC
or to be open.
CASE 3: FLASH MEMORY POWER SUPPLY IS
TURNED OFF (F-V
CC
= 0 V)
Fix RP LOW level before turning off Flash memory
power supply.
SRAM inputs and input/outputs except S-CE need to
be applied with voltages in the range of -0.3 V to
S-V
CC
+ 0.3 V or to be open (HIGH-Z).
Flash Memory inputs and input/outputs except RP
need to be applied with voltages in the range of
-0.3 V to S-V
CC
+ 0.3 V or to be open (HIGH-Z).
Power Up Sequence
When turning on Flash memory power supply, keep
RP LOW. After F-V
CC
reaches over 2.7 V, keep RP
LOW for more than 100 ns.
Device Decoupling
The power supply needs to be designed carefully
because one of the SRAM and the Flash Memory is in
standby mode when the other is active. A careful
decoupling of power supplies is necessary between
SRAM and Flash Memory. Note peak current caused
by transition of control signals (F-CE, S-CE).
NOTES:
1. F-CE should not be LOW when S-CE is LOW simultaneously.
2. X can be V
IL
or V
IH
for control pins and addresses, and V
PPLK
or V
PPH
for F-V
PP
. See DC Characteristics for V
PPLK
and V
PPH
voltages.
3. Refer to DC Characteristics. When F-V
PP
≤
V
PPLK
, memory con-
tents can be read, but not altered.
4. Do not use in a timing that both F-OE and F-WE is LOW level.
5. F-RP at GND ± 0.2 V ensures the lowest deep power down current.
6. Command writes involving block erase, write, or lock-bit configura-
tion are reliably executed when F-V
PP
= V
PPH
and F-V
CC
= V
CC1
block erase or word write operations with V
IH
< F-RP < V
HH
or
T
A
< -30
°
C produce spurious results and should not be attempted.
7. Refer to Table 6 for valid D
IN
during a write operation.
Table 2. Truth Table
1,2
F-CE
F-OE
F-WE
F-RP
S-CE
S-OE
S-WE
ADDRESS
MODE
I/O
0
to
I/O
15
Output
HIGH-Z
Input
Output
HIGH-Z
Input
HIGH-Z
HIGH-Z
CURRENT
NOTE
L
L
L
H
H
H
H
X
L
H
H
X
X
X
X
X
H
H
L
X
X
X
X
X
H
H
H
X
X
X
H
L
H
H
H
L
L
L
H
H
X
X
X
L
H
X
X
X
X
X
X
H
H
L
X
X
X
X
X
X
X
X
X
X
Flash read
Flash read
Flash write
SRAM read
SRAM read
SRAM write
Standby
Deep power down
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
I
SB
I
SB
3, 4
5
4, 6, 7
5
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