參數(shù)資料
型號: LRS1341
廠商: Sharp Corporation
英文描述: Stacked Chip 16M Flash Memory and 2M SRAM
中文描述: 堆疊芯片1,600快閃記憶體以及2M SRAM
文件頁數(shù): 1/24頁
文件大小: 197K
代理商: LRS1341
Data Sheet
1
LRS1341/LRS1342
Stacked Chip
16M Flash Memory and 2M SRAM
Data Sheet
FEATURES
Flash Memory and SRAM
Stacked Die Chip Scale Package
72-ball CSP (FBGA072-P-0811) plastic package
Power supply: 2.7 V to 3.6 V
Operating temperature: -25°C to +85°C
Flash Memory
– Access time (MAX.): 100 ns
– Operating current (MAX.):
The current for F-V
CC
pin
– Read: 25 mA (t
CYCLE
= 200 ns)
– Word write: 17 mA
– Block erase: 17 mA
– Deep power down current (the current for
F-V
CC
pin): 10 μA (MAX. F-CE
F-V
CC
- 0.2 V,
F-RP
-0.2 V, F-V
PP
0.2 V)
– Optimized array blocking architecture
– Two 4K-word boot blocks
– Six 4K-word parameter blocks
– Thirty-one 32K-word main blocks
– Top/Bottom boot location versions
– Extended cycling capability
– 100,000 block erase cycles
– Enhanced automated suspend options
– Word write suspend to read
– Block erase suspend to word write
– Block erase suspend to read
SRAM
– Access time (MAX.): 85 ns
– Operating current (MAX.):
– 45 mA
– 8 mA (t
RC
, t
WC
= 1 μs)
– Standby current: 45 μA (MAX.)
– Data retention current: 35 μA (MAX.)
DESCRIPTION
The LRS1341/LRS1342 is a combination memory
organized as 1,048,576 × 16-bit flash memory and
131,072 × 16-bit static RAM in one package.
PIN CONFIGURATION
Figure 1. LRS1341/LRS1342 Pin Configuration
A
INDEX
A
11
A
15
NC
NC
NC
A
14
A
9
1
2
3
4
5
6
7
A
16
DQ
15
DQ
14
S-V
CC
A
8
A
10
T
1
T
3
DQ
13
DQ
12
GND
T
4
F-WE
F-RY/
BY
F-RP
T
2
F-WP
F-V
PP
F-A
19
DQ
11
T
5
B
C
D
E
F
S-LB
S-UB
S-OE
NC
DQ
9
8
DQ
6
DQ
10
DQ
8
F-A
18
F-A
17
A
7
A
6
A
3
A
2
NC
NC
G
H
NC
A
5
A
4
A
0
F-OE
F-CE
GND
NC
NC
A
12
A
13
9
10
S-WE
DQ
4
S-CE
2
DQ
2
DQ
0
11
A
1
NC
NC
NC
12
DQ
7
DQ
5
F-V
CC
DQ
3
DQ
1
S-CE
1
NC
LRS1342-1
TOP VIEW
72-BALL FBGA
NOTE:
Two NC pins at the corner are connected.
GND
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