參數(shù)資料
型號(hào): LSIFC919
英文描述: LSIFC919 Single Channel Fibre Channel I/O Processor technical manual v2.0 10/01
中文描述: LSIFC919單通道光纖通道I / O處理器技術(shù)手冊(cè)2.0 10/01
文件頁數(shù): 135/144頁
文件大小: 1496K
代理商: LSIFC919
Index
IX-3
PCI (Cont.)
configuration space
5-1
device base address
5-2
interface
1-6
output signals
6-3
target disconnect
5-6
target retry
5-5
PCI cache mode
memory read line command
5-6
memory write and invalidate command
5-4
PCICLK
4-3
PERR/
4-6
,
5-10
point-to-point topology
2-8
ports
2-7
power management configuration
(PMCap) (NIPtr) (CapID)
5-21
power management control/status
(PMData) (PMCSR-BSE) (PMCtrl/St)
5-22
power state (PWS[1:0])
5-23
prefetchable memory block (prefetch)
5-15
processor
ARM RISC
1-5
,
1-6
,
1-7
I/O
1-6
protocol
channel
2-1
fibre channel (FCP)
1-1
,
2-6
internet
2-1
signaling
2-2
transmission
2-2
upper layer
2-1
,
2-3
PWS[1:0]
5-23
R
RAMCS/
4-10
RBC[1:0]
4-7
received target abort (RTA)
5-10
receiver
1-7
REFCLK
4-8
reference specifications
B-1
register map
A-1
A-2
reply
interrupt (RI)
5-28
interrupt mask (RIM)
5-29
MFA (RepMFA)
5-30
REQ/
4-3
REQ64/
4-3
request MFA (ReqMFA)
5-30
request status
1-7
reset adapter (RA)
5-27
response sequence
2-7
revision ID (RevID)
5-12
ROMSIZE [1:0]
4-10
RST/
4-3
RX[9:0]
4-7
RXLOS
4-7
RXNEG
4-8
RXPOS
4-8
S
SCL
4-12
SDA
4-12
sequences transfer
2-2
SERR/
4-6
5-11
SERR/ Enable (SERR)
5-11
shared memory
5-31
signaled system error (SSE)
5-9
signaling protocol
2-2
SSRAM Memory
3-9
start-of-frame (SOF)
2-4
status/command register
5-9
STOP/
4-5
support components
flash ROM
3-10
serial EEPROM
3-10
SSRAM Memory
3-9
system interface
1-6
T
target operation
1-7
target response
2-7
TBC
4-7
TCK_CHIP
4-13
TCK_ICE2
4-13
TDI_CHIP
4-13
TDI_ICE2
4-14
TDO_CHIP
4-13
TDO_ICE2
4-14
test base address (TBAddr)
5-27
TESTRESET/
4-11
timing diagram
64-bit dual address cycle
6-15
64-bit initiator and 64-bit target (read)
6-14
,
6-15
back-to-back (read)
6-11
back-to-back (write)
6-12
burst (read)
6-13
burst (write)
6-14
FC 10-bit and OLC transmit
6-19
FC 10-bit receive
6-18
FC OLC receive
6-17
flash ROM read
6-21
,
6-23
,
6-25
flash ROM write
6-26
TMS_CHIP
4-13
TMS_ICE1
4-13
TMS_ICE2
4-14
topology
arbitrated loop
2-8
fabric
2-8
point-to-point
2-8
transceiver
1-7
transfer
exchanges
2-2
frames
2-2
sequences
2-2
transmission protocol
2-2
transmitter
1-7
TRDY/
4-5
TRST_CHIP/
4-13
TRST_ICE2/
4-13
TTL interrupt (TTLI)
5-26
TX[9:0]
4-7
TXNEG
4-8
TXPOS
4-8
typical implementation
1-4
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