- 您現在的位置：買賣IC網 > PDF目錄369842 > LSIFC919 LSIFC919 Single Channel Fibre Channel I/O Processor technical manual v2.0 10/01 PDF資料下載
參數資料
| 型號： | LSIFC919 |
| 英文描述： | LSIFC919 Single Channel Fibre Channel I/O Processor technical manual v2.0 10/01 |
| 中文描述： | LSIFC919單通道光纖通道I / O處理器技術手冊2.0 10/01 |
| 文件頁數： | 61/144頁 |
| 文件大小： | 1496K |
| 代理商： | LSIFC919 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁當前第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁
PCI Cache Mode
5-5
The PCI configuration
Command
register, bit 4 must be set.
The
Cache Line Size
register must contain a legal burst size (2, 4,
8, 16, 32, 64, or 128) value.
The chip must have enough bytes in the DMA FIFO to complete at
least one full cache line burst.
The chip must be aligned to a cache line boundary.
When these conditions have been met, the LSIFC909 issues a Write and
Invalidate command instead of a Memory Write command during all PCI
write cycles.
5.3.3.2 Multiple Cache Line Transfers
The Write and Invalidate command can write multiple cache lines of data
in a single bus ownership. The chip issues a burst transfer as soon as it
reaches a cache line boundary. The size of the transfer is not
automatically the cache line size, but rather a multiple of the cache line
size as allowed for in Revision 2.1 of the PCI specification. The logic
selects the largest multiple of the cache line size based on the amount
of data to transfer.
When the DMA buffer contains less data than the value specified in the
Cache Line Size
register, the LSIFC909 throttles back to a Memory Write
command on the next cache line boundary.
5.3.3.3 Latency
In accordance with the PCI specification, the chip's latency timer is
ignored when issuing a Write and Invalidate command such that when a
latency time-out has occurred, the LSIFC909 continues to transfer up
until a cache line boundary. At that point, the chip relinquishes the bus,
and finishes the transfer at a later time using another bus ownership. If
the chip is transferring multiple cache lines it continues to transfer until
the next cache boundary is reached.
5.3.3.4 PCI Target Retry
During a Write and Invalidate transfer, if the target device issues a retry
(STOP with no TRDY, indicating that no data was transferred), the
LSIFC909 relinquishes the bus and immediately tries to finish the
相關PDF資料 |
PDF描述 |
|---|---|
| LSIFC929 | LSIFC929 dual channel fibre solutions |
| LSIFC929X | LSIFC929X dual channel fibre solutions |
| LSIU160 | LSIU160 Ultra160 SCSI host adapter |
| LSIU40HVD | LSIU40HVD PCI to Dual Channel SCSI host adapter user＇s guide v2.2 8/02 |
| LSIU40SE | LSIU40SE Dual Channel PCI to Ultra SCSI host adapter user＇s guide v2.2 8/02 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| LSIFC919-329BGA | 制造商:LSI Corporation 功能描述:Fiber Controller 329-Pin BGA |
| LSIFC919X | 制造商:LSI Corporation 功能描述:456PBGA LSI APPROVES CUST - Bulk |
| LSIFC929 | 制造商:LSI Corporation 功能描述:2G PCI DUAL CHANNEL FC CTL - Bulk |
| LSIFC929-329BGA | 制造商:LSI Corporation 功能描述:Fiber Controller 456-Pin BGA |
| LSIFC929X | 制造商:LSI Corporation 功能描述:- Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復。