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參數(shù)資料
| 型號： | LT1970IFE#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 21/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OP AMP 500MA ADJ 20-TSSOP |
| 標準包裝： | 74 |
| 放大器類型： | 通用 |
| 電路數(shù)： | 1 |
| 轉(zhuǎn)換速率： | 1.6 V/µs |
| 增益帶寬積： | 3.6MHz |
| 電流 - 輸入偏壓： | 160nA |
| 電壓 - 輸入偏移： | 200µV |
| 電流 - 電源： | 7mA |
| 電流 - 輸出 / 通道： | 800mA |
| 電壓 - 電源，單路/雙路(±)： | 5 V ~ 36 V，±2.5 V ~ 18 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬）裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP-EP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1320 (CN2011-ZH PDF) |
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LT1970
4
1970fc
ELECTRICAL CHARACTERISTICS The l denotes the specications which apply over the full operating
temperature range, otherwise specications are at TA = 25°C. See Test Circuit for standard test conditions.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Current Sense Bandwidth
2
MHz
RCSF
Resistance FILTER to SENSE–
l
750
1000
1250
Ω
Logic I/O Characteristics
Logic Output Leakage ISRC, ISNK, TSD
V = 15V
l
1μA
Logic Low Output Level
I = 5mA (Note 6)
l
0.2
0.4
V
Logic Output Current Limit
25
mA
VENABLE
Enable Logic Threshold
l
0.8
1.9
2.5
V
IENABLE
Enable Pin Bias Current
l
–1
1
μA
ISUPPLY
Total Supply Current
VCC, V+ and V–, VEE Connected
l
713
mA
ICC
VCC Supply Current
VCC, V+ and V–, VEE Separate
l
37
mA
ICC(STBY)
Supply Current Disabled
VCC, V+ and V–, VEE Connected, VENABLE ≤ 0.8V
l
0.6
1.5
mA
tON
Turn-On Delay
(Note 7)
10
μs
tOFF
Turn-Off Delay
(Note 7)
10
μs
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device reli-
ability and lifetime.
Note 2: The LT1970C is guaranteed functional over the operating tempera-
ture range of – 40°C and 85°C.
Note 3: The LT1970C is guaranteed to meet specied performance from
0°C to 70°C. The LT1970C is designed, characterized and expected to
meet specied performance from –40°C to 85°C but is not tested or QA
sampled at these temperatures. The LT1970I is guaranteed to meet speci-
ed performance from –40°C to 85°C.
Note 4: This parameter is not 100% tested.
Note 5: Full power bandwidth is calculated from slew rate measurements:
FPBW = SR/(2 π VP)
Note 6: The logic low output level of pin TSD is guaranteed by correlating
the output level of pin ISRC and pin ISNK over temperature.
Note 7: Turn-on and turn-off delay are measured from VENABLE crossing
1.6V to the OUT pin at 90% of normal output voltage.
Note 8: Thermal resistance varies depending upon the amount of PC board
metal attached to the device. If the maximum dissipation of the package is
exceeded, the device will go into thermal shutdown and be protected.
Warm-Up Drift VIO vs Time
Input Bias Current vs VCM
Total Supply Current
vs Supply Voltage
TYPICAL PERFORMANCE CHARACTERISTICS
TIME (100ms/DIV)
1970 G01
0V
V
OS
1000
(50mV/DIV)
COMMON MODE INPUT VOLTAGE (V)
–15 –12 –9 –6 –3
0
3
6
9
12 15
INPUT
BIAS
CURRENT
(nA)
–100
–120
–140
–160
–180
–200
–220
–240
–260
1970 G02
VS = ±15V
–IBIAS
+IBIAS
SUPPLY VOLTAGE (±V)
0
–14
TOTAL
SUPPLY
CURRENT
(mA)
–10
–6
–2
14
6
4
8
10
18
1970 G03
10
2
–12
–8
–4
12
4
8
0
26
12
14
16
ICC + IV+
IEE + IV–
25°C
–55°C
125°C
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